sram_test.map.rpt

Verilog语言对SRAM的操作,也提一些简单的快速操作SRAM的技巧。

+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 89    ;
;     -- Combinational with no register       ; 30    ;
;     -- Register only                        ; 8     ;
;     -- Combinational with a register        ; 51    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 20    ;
;     -- 3 input functions                    ; 10    ;
;     -- 2 input functions                    ; 50    ;
;     -- 1 input functions                    ; 1     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 46    ;
;     -- arithmetic mode                      ; 43    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 59    ;
;                                             ;       ;
; Total registers                             ; 59    ;
; Total logic cells in carry chains           ; 46    ;
; I/O pins                                    ; 27    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 59    ;
; Total fan-out                               ; 392   ;
; Average fan-out                             ; 3.38  ;
+---------------------------------------------+-------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                  ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |sram_test                 ; 89 (89)     ; 59           ; 0          ; 27   ; 0            ; 30 (30)      ; 8 (8)             ; 51 (51)          ; 46 (46)         ; 0 (0)      ; |sram_test          ; work         ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------+
; State Machine - |sram_test|cstate                                                 ;
+-------------+-------------+-------------+-------------+-------------+-------------+
; Name        ; cstate.REA0 ; cstate.WRT1 ; cstate.WRT0 ; cstate.IDLE ; cstate.REA1 ;
+-------------+-------------+-------------+-------------+-------------+-------------+
; cstate.IDLE ; 0           ; 0           ; 0           ; 0           ; 0           ;
; cstate.WRT0 ; 0           ; 0           ; 1           ; 1           ; 0           ;
; cstate.WRT1 ; 0           ; 1           ; 0           ; 1           ; 0           ;
; cstate.REA0 ; 1           ; 0           ; 0           ; 1           ; 0           ;
; cstate.REA1 ; 0           ; 0           ; 0           ; 1           ; 1           ;
+-------------+-------------+-------------+-------------+-------------+-------------+


+-----------------------------------------------------------------+
; Registers Removed During Synthesis                              ;
+----------------------------------------+------------------------+
; Register name                          ; Reason for Removal     ;
+----------------------------------------+------------------------+
; addr_r[0]                              ; Merged with wr_data[0] ;
; addr_r[1]                              ; Merged with wr_data[1] ;
; addr_r[2]                              ; Merged with wr_data[2] ;
; addr_r[3]                              ; Merged with wr_data[3] ;
; addr_r[4]                              ; Merged with wr_data[4] ;
; addr_r[5]                              ; Merged with wr_data[5] ;
; addr_r[6]                              ; Merged with wr_data[6] ;
; addr_r[7]                              ; Merged with wr_data[7] ;
; cstate~14                              ; Lost fanout            ;
; cstate~15                              ; Lost fanout            ;
; cstate~17                              ; Lost fanout            ;
; Total Number of Removed Registers = 11 ;                        ;
+----------------------------------------+------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 59    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 59    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 22    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |sram_test ;
+----------------+-------+--------------------------------------------------+
; Parameter Name ; Value ; Type                                             ;
+----------------+-------+--------------------------------------------------+
; IDLE           ; 0000  ; Unsigned Binary                                  ;
; WRT0           ; 0001  ; Unsigned Binary                                  ;
; WRT1           ; 0010  ; Unsigned Binary                                  ;
; REA0           ; 0011  ; Unsigned Binary                                  ;
; REA1           ; 0100  ; Unsigned Binary                                  ;
+----------------+-------+--------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
    Info: Processing started: Thu Feb 12 09:21:02 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sram_test -c sram_test
Info: Found 1 design units, including 1 entities, in source file sram_test.v
    Info: Found entity 1: sram_test
Info: Elaborating entity "sram_test" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at sram_test.v(40): truncated value with size 32 to match size of target (26)
Info (10264): Verilog HDL Case Statement information at sram_test.v(119): all case item expressions in this case statement are onehot
Info: 3 registers lost all their fanouts during netlist optimizations. The first 3 are displayed below.
    Info: Register "cstate~14" lost all its fanouts during netlist optimizations.
    Info: Register "cstate~15" lost all its fanouts during netlist optimizations.
    Info: Register "cstate~17" lost all its fanouts during netlist optimizations.
Info: Implemented 116 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 17 output pins
    Info: Implemented 8 bidirectional pins
    Info: Implemented 89 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 165 megabytes
    Info: Processing ended: Thu Feb 12 09:21:04 2009
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:02