txmitt.v

hi this is reference code for UART use UAER0_3

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// Copyright (c) 2001 - 2008 by Lattice Semiconductor Corporation
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// in synthesis for any Lattice programmable logic product. Other
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//
// This VHDL or Verilog source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
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// regarding the use or functionality of this code.
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// Code Revision History :
// --------------------------------------------------------------------
// Ver: | Author |Mod. Date |Changes Made:
// V1.0 |        |          | Initial ver
// V1.1 | S.R.   |18/12/08  | modified to support Mico8
// --------------------------------------------------------------------

`ifndef TXMITT_FILE
`define TXMITT_FILE
`timescale 1ns/10ps
`include "system_conf.v"
module txmitt #(parameter DATAWIDTH = 16,
                parameter FIFO = 0) 
  (  
  reset,         // Global reset and clock
  clk,      
  thr,           // Register THR                    
  thr_wr,        // THR write strobe 
  sout,          // Transmitter output              
  databits,      // Transmitter control             
  stopbits,      
  parity_en,     
  parity_even,   
  parity_stick,  
  tx_break,      
  thre,          // Transmitter status  
  temt,
  fifo_empty_thr,
  thr_rd,
  divisor);

  input    reset ;
  input    clk   ;
  input [DATAWIDTH-1 :0]   thr;
                 
  input                    thr_wr ;
  input [1:0]              databits;
  input [1:0]              stopbits;
  input                    parity_en;
  input                    parity_even ;
  input                    parity_stick; 
  input                    tx_break ;
  input                    fifo_empty_thr;
  output                   thr_rd;
                 
  output                   thre;
  output                   temt;
  output                   sout;
  input [15:0]             divisor;
  
  reg                      tx_output;
  reg [DATAWIDTH-1 :0]     tsr;
  reg                      tx_parity;
  reg                      thr_empty;
  reg                      tsr_empty;
  reg                      tx_in_start_s;
  reg                      tx_in_shift_s;
  reg                      tx_in_stop_s;
  reg                      tx_in_shift_s1; //tx_in_shift_s delayed 1 clock
  reg                      tx_in_stop_s1; //tx_in_stop_s delayed 1 clock
  reg                      txclk_ena;
  reg                      txclk_enb;
  reg [2:0]                tx_cnt;
  reg [3:0]                count_v;
  reg                      thr_rd_int;
  reg                      thr_rd_delay;
  reg                      last_word;
  
  // State Machine Definition
  parameter start        = 3'b000;
  parameter shift        = 3'b001;
  parameter parity       = 3'b010;
  parameter stop_1bit    = 3'b011;
  parameter stop_2bit    = 3'b100;
  parameter stop_halfbit = 3'b101;
  parameter start1       = 3'b110; 
 
  reg [2:0] tx_state;
  reg [15:0] counter;
  wire [15:0] divisor_2;
  assign divisor_2 = divisor/2;

 generate 
   if (FIFO == 1)  
   // Generate Single cycle THR FIFO read signal 
   always @(posedge clk or posedge reset)
     if (reset)
       thr_rd_delay <= 1'b0;
     else
       thr_rd_delay <= thr_rd_int;
   assign thr_rd = thr_rd_int & ~thr_rd_delay; 	     
 endgenerate

   ////////////////////////////////////////////////////////////////////////////////
   // Transmitter Finite State Machine
   ////////////////////////////////////////////////////////////////////////////////

   generate
   begin
      if (FIFO == 1)
      begin

     always @(posedge clk or posedge reset) begin
     if (reset) 
       thr_rd_int <= 1'b0;
     else begin
       if ((tx_state == start) && (!fifo_empty_thr) && !thr_rd_int)
         thr_rd_int <= 1'b1;
       else if (tx_state == shift)
	 thr_rd_int <= 1'b0;      
     end
     end

     always @(posedge clk or posedge reset) begin
     if (reset) begin
          tx_cnt    <= 0;
          tsr       <= 0;
          tx_output <= 1'b1;
          tx_parity <= 1'b1;
          tx_state  <= start; 
          last_word <= 1'b0;
          counter   <= 16'b0000000000000000;end 
     else begin
        case (tx_state)

  start:  
	if (thr_rd_delay)   
	  tx_state <= start1;
	  
  start1: begin
             if (last_word)
		  last_word <= 1'b0;
            if ( ~|counter)
	      counter <= divisor;
            else begin
	      if (counter == 16'b0000_0000_0000_0001) begin
		 counter <= 0;
	         tx_state <= shift;
                 tx_parity <= ~parity_even;  // TxParity initialization
                 tx_cnt <= 0;		
		 tsr <= thr;
	      end
              else
	        counter <= counter - 1'b1;
	     end
              tx_output <= 1'b0;	
         end

	 shift: begin
	     tx_output <= tsr[0];	 
	     if ( ~|counter)
	      counter <= divisor;
             else begin
	      if (counter == 16'b0000_0000_0000_0001) begin
		tx_parity <= tx_parity ^ tsr[0];
		counter <= 0;      
                tsr <= {1'b0, tsr[7:1]};      // Shift serial data out
                tx_cnt <= tx_cnt + 1;
                if ((databits==2'b00 && tx_cnt==3'h4) || 
                    (databits==2'b01 && tx_cnt==3'h5) || 
                    (databits==2'b10 && tx_cnt==3'h6) || 
                    (databits==2'b11 && tx_cnt==3'h7))   
                    tx_state <= (parity_en) ? parity : stop_1bit;
                end
	      else 
	        counter <= counter - 1'b1;
             end
           end 	     
	  parity: begin
            if ( ~|counter)
	      counter <= divisor;
             else begin
	      if (counter == 16'b0000_0000_0000_0001) begin
		counter <= 0;
                tx_state <= stop_1bit;
              end
	      else
		counter <= counter - 1'b1;
             end
             tx_output <= (parity_stick) ? (~parity_even) : tx_parity;
           end 	     
              
	   stop_1bit: begin
             if ( ~|counter)
	      counter <= divisor;
             else begin
	      if (counter == 16'b0000_0000_0000_0001) begin
		counter <= 0; 
                if (fifo_empty_thr)
	          last_word <= 1'b1;
                if (stopbits == 2'b00)      // 1 stop bit 
		   tx_state <= start; 	   
                else if (stopbits == 2'b01) // 1.5 stop bits(for 5-bit data only)
                   tx_state <= stop_halfbit;
                else
                   tx_state <= stop_2bit;    // 2 stop bits(for 6,7,8-bit data)
              end
	      else
		counter <= counter - 1'b1;
             end 	
             tx_output  <= 1'b1;
           end		   
   
	   stop_2bit: begin
             if ( ~|counter)
	      counter <= divisor;
             else begin
	      if (counter == 16'b0000_0000_0000_0001) begin
		counter <= 0;
                tx_state <= start;
	      end
              else
	        counter <= counter - 1'b1;
             end
              tx_output <= 1'b1;	     
           end		   
          
	   stop_halfbit: begin
             if ( ~|counter)
	      counter <= divisor_2;
             else begin
	      if (counter == 16'b0000_0000_0000_0001) begin