📄 io_map.h
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byte ID1 :1; /* Part ID Register Bit 1 */
byte ID2 :1; /* Part ID Register Bit 2 */
byte ID3 :1; /* Part ID Register Bit 3 */
byte ID4 :1; /* Part ID Register Bit 4 */
byte ID5 :1; /* Part ID Register Bit 5 */
byte ID6 :1; /* Part ID Register Bit 6 */
byte ID7 :1; /* Part ID Register Bit 7 */
} Bits;
struct {
byte grpID :8;
} MergedBits;
} PARTIDLSTR;
extern volatile PARTIDLSTR _PARTIDL @(REG_BASE + 0x0000001B);
#define PARTIDL _PARTIDL.Byte
#define PARTIDL_ID0 _PARTIDL.Bits.ID0
#define PARTIDL_ID1 _PARTIDL.Bits.ID1
#define PARTIDL_ID2 _PARTIDL.Bits.ID2
#define PARTIDL_ID3 _PARTIDL.Bits.ID3
#define PARTIDL_ID4 _PARTIDL.Bits.ID4
#define PARTIDL_ID5 _PARTIDL.Bits.ID5
#define PARTIDL_ID6 _PARTIDL.Bits.ID6
#define PARTIDL_ID7 _PARTIDL.Bits.ID7
#define PARTIDL_ID _PARTIDL.MergedBits.grpID
#define PARTIDL_ID0_MASK 1
#define PARTIDL_ID1_MASK 2
#define PARTIDL_ID2_MASK 4
#define PARTIDL_ID3_MASK 8
#define PARTIDL_ID4_MASK 16
#define PARTIDL_ID5_MASK 32
#define PARTIDL_ID6_MASK 64
#define PARTIDL_ID7_MASK 128
#define PARTIDL_ID_MASK 255
#define PARTIDL_ID_BITNUM 0
/*** MEMSIZ0 - Memory Size Register Zero; 0x0000001C ***/
typedef union {
byte Byte;
struct {
byte ram_sw0 :1; /* Allocated RAM Memory Space Bit 0 */
byte ram_sw1 :1; /* Allocated RAM Memory Space Bit 1 */
byte ram_sw2 :1; /* Allocated RAM Memory Space Bit 2 */
byte :1;
byte eep_sw0 :1; /* Allocated EEPROM Memory Space Bit 0 */
byte eep_sw1 :1; /* Allocated EEPROM Memory Space Bit 1 */
byte :1;
byte reg_sw0 :1; /* Allocated System Register Space */
} Bits;
struct {
byte grpram_sw :3;
byte :1;
byte grpeep_sw :2;
byte :1;
byte grpreg_sw :1;
} MergedBits;
} MEMSIZ0STR;
extern volatile MEMSIZ0STR _MEMSIZ0 @(REG_BASE + 0x0000001C);
#define MEMSIZ0 _MEMSIZ0.Byte
#define MEMSIZ0_ram_sw0 _MEMSIZ0.Bits.ram_sw0
#define MEMSIZ0_ram_sw1 _MEMSIZ0.Bits.ram_sw1
#define MEMSIZ0_ram_sw2 _MEMSIZ0.Bits.ram_sw2
#define MEMSIZ0_eep_sw0 _MEMSIZ0.Bits.eep_sw0
#define MEMSIZ0_eep_sw1 _MEMSIZ0.Bits.eep_sw1
#define MEMSIZ0_reg_sw0 _MEMSIZ0.Bits.reg_sw0
#define MEMSIZ0_ram_sw _MEMSIZ0.MergedBits.grpram_sw
#define MEMSIZ0_eep_sw _MEMSIZ0.MergedBits.grpeep_sw
#define MEMSIZ0_ram_sw0_MASK 1
#define MEMSIZ0_ram_sw1_MASK 2
#define MEMSIZ0_ram_sw2_MASK 4
#define MEMSIZ0_eep_sw0_MASK 16
#define MEMSIZ0_eep_sw1_MASK 32
#define MEMSIZ0_reg_sw0_MASK 128
#define MEMSIZ0_ram_sw_MASK 7
#define MEMSIZ0_ram_sw_BITNUM 0
#define MEMSIZ0_eep_sw_MASK 48
#define MEMSIZ0_eep_sw_BITNUM 4
/*** MEMSIZ1 - Memory Size Register One; 0x0000001D ***/
typedef union {
byte Byte;
struct {
byte pag_sw0 :1; /* Allocated Off-Chip Memory Options Bit 0 */
byte pag_sw1 :1; /* Allocated Off-Chip Memory Options Bit 1 */
byte :1;
byte :1;
byte :1;
byte :1;
byte rom_sw0 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 0 */
byte rom_sw1 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 1 */
} Bits;
struct {
byte grppag_sw :2;
byte :1;
byte :1;
byte :1;
byte :1;
byte grprom_sw :2;
} MergedBits;
} MEMSIZ1STR;
extern volatile MEMSIZ1STR _MEMSIZ1 @(REG_BASE + 0x0000001D);
#define MEMSIZ1 _MEMSIZ1.Byte
#define MEMSIZ1_pag_sw0 _MEMSIZ1.Bits.pag_sw0
#define MEMSIZ1_pag_sw1 _MEMSIZ1.Bits.pag_sw1
#define MEMSIZ1_rom_sw0 _MEMSIZ1.Bits.rom_sw0
#define MEMSIZ1_rom_sw1 _MEMSIZ1.Bits.rom_sw1
#define MEMSIZ1_pag_sw _MEMSIZ1.MergedBits.grppag_sw
#define MEMSIZ1_rom_sw _MEMSIZ1.MergedBits.grprom_sw
#define MEMSIZ1_pag_sw0_MASK 1
#define MEMSIZ1_pag_sw1_MASK 2
#define MEMSIZ1_rom_sw0_MASK 64
#define MEMSIZ1_rom_sw1_MASK 128
#define MEMSIZ1_pag_sw_MASK 3
#define MEMSIZ1_pag_sw_BITNUM 0
#define MEMSIZ1_rom_sw_MASK 192
#define MEMSIZ1_rom_sw_BITNUM 6
/*** INTCR - Interrupt Control Register; 0x0000001E ***/
typedef union {
byte Byte;
struct {
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte IRQEN :1; /* External IRQ Enable */
byte IRQE :1; /* IRQ Select Edge Sensitive Only */
} Bits;
} INTCRSTR;
extern volatile INTCRSTR _INTCR @(REG_BASE + 0x0000001E);
#define INTCR _INTCR.Byte
#define INTCR_IRQEN _INTCR.Bits.IRQEN
#define INTCR_IRQE _INTCR.Bits.IRQE
#define INTCR_IRQEN_MASK 64
#define INTCR_IRQE_MASK 128
/*** HPRIO - Highest Priority I Interrupt; 0x0000001F ***/
typedef union {
byte Byte;
struct {
byte :1;
byte PSEL1 :1; /* Highest Priority I Interrupt Bit 1 */
byte PSEL2 :1; /* Highest Priority I Interrupt Bit 2 */
byte PSEL3 :1; /* Highest Priority I Interrupt Bit 3 */
byte PSEL4 :1; /* Highest Priority I Interrupt Bit 4 */
byte PSEL5 :1; /* Highest Priority I Interrupt Bit 5 */
byte PSEL6 :1; /* Highest Priority I Interrupt Bit 6 */
byte PSEL7 :1; /* Highest Priority I Interrupt Bit 7 */
} Bits;
struct {
byte :1;
byte grpPSEL_1 :7;
} MergedBits;
} HPRIOSTR;
extern volatile HPRIOSTR _HPRIO @(REG_BASE + 0x0000001F);
#define HPRIO _HPRIO.Byte
#define HPRIO_PSEL1 _HPRIO.Bits.PSEL1
#define HPRIO_PSEL2 _HPRIO.Bits.PSEL2
#define HPRIO_PSEL3 _HPRIO.Bits.PSEL3
#define HPRIO_PSEL4 _HPRIO.Bits.PSEL4
#define HPRIO_PSEL5 _HPRIO.Bits.PSEL5
#define HPRIO_PSEL6 _HPRIO.Bits.PSEL6
#define HPRIO_PSEL7 _HPRIO.Bits.PSEL7
#define HPRIO_PSEL_1 _HPRIO.MergedBits.grpPSEL_1
#define HPRIO_PSEL HPRIO_PSEL_1
#define HPRIO_PSEL1_MASK 2
#define HPRIO_PSEL2_MASK 4
#define HPRIO_PSEL3_MASK 8
#define HPRIO_PSEL4_MASK 16
#define HPRIO_PSEL5_MASK 32
#define HPRIO_PSEL6_MASK 64
#define HPRIO_PSEL7_MASK 128
#define HPRIO_PSEL_1_MASK 254
#define HPRIO_PSEL_1_BITNUM 1
/*** DBGC1 - Debug Control Register 1; 0x00000020 ***/
typedef union {
byte Byte;
struct {
byte CAPMOD0 :1; /* Capture Mode Field, bit 0 */
byte CAPMOD1 :1; /* Capture Mode Field, bit 1 */
byte :1;
byte DBGBRK :1; /* DBG Breakpoint Enable Bit */
byte BEGIN :1; /* Begin/End Trigger Bit */
byte TRGSEL :1; /* Trigger Selection Bit */
byte ARM :1; /* Arm Bit */
byte DBGEN :1; /* DBG Mode Enable Bit */
} Bits;
struct {
byte grpCAPMOD :2;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
} MergedBits;
} DBGC1STR;
extern volatile DBGC1STR _DBGC1 @(REG_BASE + 0x00000020);
#define DBGC1 _DBGC1.Byte
#define DBGC1_CAPMOD0 _DBGC1.Bits.CAPMOD0
#define DBGC1_CAPMOD1 _DBGC1.Bits.CAPMOD1
#define DBGC1_DBGBRK _DBGC1.Bits.DBGBRK
#define DBGC1_BEGIN _DBGC1.Bits.BEGIN
#define DBGC1_TRGSEL _DBGC1.Bits.TRGSEL
#define DBGC1_ARM _DBGC1.Bits.ARM
#define DBGC1_DBGEN _DBGC1.Bits.DBGEN
#define DBGC1_CAPMOD _DBGC1.MergedBits.grpCAPMOD
#define DBGC1_CAPMOD0_MASK 1
#define DBGC1_CAPMOD1_MASK 2
#define DBGC1_DBGBRK_MASK 8
#define DBGC1_BEGIN_MASK 16
#define DBGC1_TRGSEL_MASK 32
#define DBGC1_ARM_MASK 64
#define DBGC1_DBGEN_MASK 128
#define DBGC1_CAPMOD_MASK 3
#define DBGC1_CAPMOD_BITNUM 0
/*** DBGSC - Debug Status and Control Register; 0x00000021 ***/
typedef union {
byte Byte;
struct {
byte TRG0 :1; /* Trigger Mode Bits, bit 0 */
byte TRG1 :1; /* Trigger Mode Bits, bit 1 */
byte TRG2 :1; /* Trigger Mode Bits, bit 2 */
byte TRG3 :1; /* Trigger Mode Bits, bit 3 */
byte :1;
byte CF :1; /* Comparator C Match Flag */
byte BF :1; /* Trigger B Match Flag */
byte AF :1; /* Trigger A Match Flag */
} Bits;
struct {
byte grpTRG :4;
byte :1;
byte :1;
byte :1;
byte :1;
} MergedBits;
} DBGSCSTR;
extern volatile DBGSCSTR _DBGSC @(REG_BASE + 0x00000021);
#define DBGSC _DBGSC.Byte
#define DBGSC_TRG0 _DBGSC.Bits.TRG0
#define DBGSC_TRG1 _DBGSC.Bits.TRG1
#define DBGSC_TRG2 _DBGSC.Bits.TRG2
#define DBGSC_TRG3 _DBGSC.Bits.TRG3
#define DBGSC_CF _DBGSC.Bits.CF
#define DBGSC_BF _DBGSC.Bits.BF
#define DBGSC_AF _DBGSC.Bits.AF
#define DBGSC_TRG _DBGSC.MergedBits.grpTRG
#define DBGSC_TRG0_MASK 1
#define DBGSC_TRG1_MASK 2
#define DBGSC_TRG2_MASK 4
#define DBGSC_TRG3_MASK 8
#define DBGSC_CF_MASK 32
#define DBGSC_BF_MASK 64
#define DBGSC_AF_MASK 128
#define DBGSC_TRG_MASK 15
#define DBGSC_TRG_BITNUM 0
/*** DBGTB - Debug Trace Buffer Register; 0x00000022 ***/
typedef union {
word Word;
/* Overlapped registers: */
struct {
/*** DBGTBH - Debug Trace Buffer Register High; 0x00000022 ***/
union {
byte Byte;
struct {
byte BIT8 :1; /* Trace Buffer Data Bit 8 */
byte BIT9 :1; /* Trace Buffer Data Bit 9 */
byte BIT10 :1; /* Trace Buffer Data Bit 10 */
byte BIT11 :1; /* Trace Buffer Data Bit 11 */
byte BIT12 :1; /* Trace Buffer Data Bit 12 */
byte BIT13 :1; /* Trace Buffer Data Bit 13 */
byte BIT14 :1; /* Trace Buffer Data Bit 14 */
byte BIT15 :1; /* Trace Buffer Data Bit 15 */
} Bits;
struct {
byte grpBIT_8 :8;
} MergedBits;
} DBGTBHSTR;
#define DBGTBH _DBGTB.Overlap_STR.DBGTBHSTR.Byte
#define DBGTBH_BIT8 _DBGTB.Overlap_STR.DBGTBHSTR.Bits.BIT8
#define DBGTBH_BIT9 _DBGTB.Overlap_STR.DBGTBHSTR.Bits.BIT9
#define DBGTBH_BIT10 _DBGTB.Overlap_STR.DBGTBHSTR.Bits.BIT10
#define DBGTBH_BIT11 _DBGTB.Overlap_STR.DBGTBHSTR.Bits.BIT11
#define DBGTBH_BIT12 _DBGTB.Overlap_STR.DBGTBHSTR.Bits.BIT12
#define DBGTBH_BIT13 _DBGTB.Overlap_STR.DBGTBHSTR.Bits.BIT13
#define DBGTBH_BIT14 _DBGTB.Overlap_STR.DBGTBHSTR.Bits.BIT14
#define DBGTBH_BIT15 _DBGTB.Overlap_STR.DBGTBHSTR.Bits.BIT15
#define DBGTBH_BIT_8 _DBGTB.Overlap_STR.DBGTBHSTR.MergedBits.grpBIT_8
#define DBGTBH_BIT DBGTBH_BIT_8
#define DBGTBH_BIT8_MASK 1
#define DBGTBH_BIT9_MASK 2
#define DBGTBH_BIT10_MASK 4
#define DBGTBH_BIT11_MASK 8
#define DBGTBH_BIT12_MASK 16
#define DBGTBH_BIT13_MASK 32
#define DBGTBH_BIT14_MASK 64
#define DBGTBH_BIT15_MASK 128
#define DBGTBH_BIT_8_MASK 255
#define DBGTBH_BIT_8_BITNUM 0
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