📄 etherinit.h
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/******************************************************************************
*
*
* File Name : etherinit.h
* Description : This file contains configuration modes for NE64 start-up
*
*
*
******************************************************************************/
#include "MOTTYPES.h"
#ifdef ETHER_INIT_H
#else
#define ETHER_INIT_H
#define WORD_ACCESS 1 /**< Word Acess Mode. This mode allows word access to buffers instead of
* byte acess to increase overall system preformance. */
#define ZERO_COPY 1 /**< Zero Copy Mode. Setting this mode not only can conserve RAM
* but can also increase performance. In this mode, no copy of the
* recieve buffer is created, so the data is processed in the buffer */
#define RX_POLL_MODE 0 /**< 1 = polling; Set to 0 to make RX interrupt driven >> Not implemented into Viola Stack */
//Mode for UNH IOL testing (Echo IEEE packets)
#define IEEE_PKT 0 /**< Mode for UNH IOL testing (Do not use for gerneral use) */
#define ON_OFF_AUTONEG 0 /**< Mode for UNH IOL testing (Do not use for gerneral use) */
#define READ_PHY_ID 0 /**< Mode for UNH IOL testing (Do not use for gerneral use) */
#define READ_ALL_REGS 0 /**< Mode for UNH IOL testing (Do not use for gerneral use) */
//PHY config defines
//=====================
#define PHY_ADDRESS 0 /**< PHY address used by the MII serial management interface */
#define BUS_CLOCK 25000000 /**< Busclock setting set be the CRG/PLL */
//PAUSE CONTROL
//=====================
//Configure support for flow control in auto neg or manually
#define XFLOWC 0 /**< 1 - enable flow control in full dueplex / 0 - disable */
#define PAUSE_TIME 5 /**< Enter value for PAUSE duration parameter in units of slot times (512 bit times) */
#define SEND_PAUSE 1 /**<define for EtherPause function ptrc variable */
#define READ_PTIME 0 /**<define for EtherPause function ptrc variable */
//LINK SPEED/DUPLEX CONTROL
//=====================
//Configure for manual or auto_neg configuration
#define AUTO_NEG 0 /**< 1 - enable AUTO_NEG / 0 - disable AUTO_NEG */
#if AUTO_NEG
//define what I addvertise in auto negotiation
#define HALF100 1 /**< Configure mode that the device should advertise in auto negotiation (advertise=1) */
#define FULL100 1 /**< Configure mode that the device should advertise in auto negotiation (advertise=1) */
#define HALF10 1 /**< Configure mode that the device should advertise in auto negotiation (advertise=1) */
#define FULL10 1 /**< Configure mode that the device should advertise in auto negotiation (advertise=1) */
//auto neg_patch
#define AUTO_NEG_TIMEOUT 0 /**< 1 - Use auto neg. patch */
#if AUTO_NEG_TIMEOUT 1
#define SPEED100_P 0 /**< 1 - enable 100 MBps / 0 - enable 10MBps */
#endif //AUTO_NEG_TIMEOUT
#else //AUTO_NEG
#define SPEED100 1 /**< 1 - enable 100 MBps / 0 - enable 10 MBps */
#define FULL_DUPLEX 0 /**< 1 - enable full duplex / 0 - disable */
#endif //AUTO_NEG
//EMAC CONTROL
//===============
//Address Filtering; RXMODE setting: PAUSE frame supported, Accept Unique, Brodcast, MultiCast
#define BRODC_REJ 0 /**< 1 = All broadcast address frames are rejected. */
#define CON_MULTIC 0 /**< 1 = Multicast hash table is used for checking multicast addresses. */
#define PROM_MODE 0 /**< 1 = All frames are received regardless of address. */
//Ethertype Control
#define ETYPE_PET 0 /**< 1 = accept Programmable Ethertype, 'etype' parameter is used */
#define ETYPE_EMW 0 /**< 1 = accept Emware Ethertype */
#define ETYPE_IPV6 0 /**< 1 = accept Internet IP version (IPV6) Ethertype */
#define ETYPE_ARP 0 /**< 1 = accept Address Resolution Protocol (ARP) Ethertype */
#define ETYPE_IPV4 0 /**< 1 = accept Internet IP version 4 (IPV6) Ethertype */
#define ETYPE_IEEE 0 /**< 1 = accept IEEE802.3 Length Field Ethertype */
#define ETYPE_ALL 1 /**< 1 = accept Accept all ethertypes. THIS OVERRIDES OTHER SETTINGS */
//Programable Ethertype
#define ETYPE_PRG 0 /**< Enter Value if ETYPE_PET is set for filter target */
//Recieve maxiuim frame length
#define RX_MAX_FL 1536 /**< Recieve maxiuim frame length */
#define DELETE_BFRAMES 0 /**< set to 1 to delete packets larger the maxiuim frame length (babbling error) */
//Register Mask and Other
//===============
/* Definition of allowed values for MDCSEL */
#define MII_MDCSEL(x) x/5000000
#define MII_WRITE 0x01
#define MII_READ 0x02
#define TCMD_START 0x01 /* Transmit buffer frame */
#define TCMD_PAUSE 0x02 /* Transmit PAUSE frame */
#define TCMD_ABORT 0x03 /* Abort transmission */
/* PHY registers symbolic names */
/* (located in MII memory map, accessible through MDIO) */
#define PHY_REG_CR 0x00 /* Control Register */
#define PHY_REG_SR 0x01 /* Status Register */
#define PHY_REG_ID1 0x02 /* PHY Identification Register 1 */
#define PHY_REG_ID2 0x03 /* PHY Identification Register 2 */
#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement Register */
#define PHY_REG_ANLPAR 0x05 /* Auto-Negotiation Link Partner Ability Register */
#define PHY_REG_ER 0x06 /* Auto-Negotiation Expansion Register */
#define PHY_REG_NPTR 0x07 /* Auto-Negotiation Next Page Transfer Register */
#define PHY_REG_IR 0x10 /* Interrupt Register */
#define PHY_REG_PSR 0x11 /* Proprietary Status Register */
#define PHY_REG_PCR 0x12 /* Proprietary Control Register */
#define PHY_REG_10BTBC 0x13 /* 10Base-T Bypass Control Register */
#define PHY_REG_100BXBC 0x14 /* 100Base-X Bypass Control Register */
#define PHY_REG_ADDR 0x15 /* Test & Trim Control Register */
#define PHY_REG_DSPRC 0x17 /* DSP Reset Control */
#define PHY_REG_DSPRR1 0x18 /* 100Base-X DSP Read Registers */
#define PHY_REG_DSPRR2 0x19
#define PHY_REG_DSPRR3 0x1A
#define PHY_REG_DSPWR1 0x1B /* 100Base-X DSP Write Registers */
#define PHY_REG_DSPWR2 0x1C
#define PHY_REG_DSPWR3 0x1D
/* PHY registers structure */
/* 0 - Control Register */
#define PHY_R0_RESET 0x8000 /* Reset */
#define PHY_R0_LB 0x4000 /* Loop Back */
#define PHY_R0_DR 0x2000 /* Data Rate (100Mb/s) */
#define PHY_R0_ANE 0x1000 /* Auto-Negotiation Enable */
#define PHY_R0_PD 0x0800 /* Power Down */
#define PHY_R0_ISOLATE 0x0400 /* Isolate (MII is disconnected) */
#define PHY_R0_RAN 0x0200 /* Restart Auto-Negotiation */
#define PHY_R0_DPLX 0x0100 /* Duplex (Full duplex) */
#define PHY_R0_CT 0x0080 /* Collision Test (Enable) */
/* 1 - Status Register */
#define PHY_R1_100T4 0x8000 /* 100BASET4 Supported */
#define PHY_R1_100F 0x4000 /* 100Mb/s Full Duplex Supported */
#define PHY_R1_100H 0x2000 /* 100Mb/s Half Duplex Supported */
#define PHY_R1_10F 0x1000 /* 10Mb/s Full Duplex Supported */
#define PHY_R1_10H 0x0800 /* 10Mb/s Half Duplex Supported */
#define PHY_R1_SUP 0x0040 /* MI Preamble Supression (capable of) */
#define PHY_R1_ANC 0x0020 /* Auto Negotiation Complete */
#define PHY_R1_RF 0x0010 /* Remote Fault */
#define PHY_R1_ANA 0x0008 /* Auto-Negotiation Ability (present) */
#define PHY_R1_LS 0x0004 /* Link Status (Link is Up) */
#define PHY_R1_JD 0x0002 /* Jabber Detect (detected) */
#define PHY_R1_EC 0x0001 /* Extended Capability (regs 2 to 31 exists) */
/* 2 - PHY Identifier Register 1 */
/* 3 - PHY Identifier Register 2 */
/* read only - contains Manufacturer's info etc.
see documentation for the detailed description */
/* 4 - Auto Negotiation Advertisement Register */
#define PHY_R4_NP 0x8000 /* Next Page (capable of sending next pages) */
#define PHY_R4_RF 0x2000 /* Remote Fault */
#define PHY_R4_FC 0x0400 /* Flow Control */
#define PHY_R4_100F 0x0100 /* 100Base-TX Full Duplex Capable */
#define PHY_R4_100H 0x0080 /* 100Base-TX Half Duplex Capable */
#define PHY_R4_10F 0x0040 /* 10Base-T Full Duplex Capable */
#define PHY_R4_10H 0x0020 /* 10Base-T Half Duplex Capable */
/* bits 4 to 0 are Selector Field (IEEE Std 802.3 = 00001) */
/* 5 - Auto Negotiation Link Partner Ability Register (Base Page & Next Page) */
/* read only - please consult PHY documentation */
#define PHY_R5_FCTL 0x0400 /* 10Base-T Half Duplex Capable */
/* 16 - Interrupt Control Register */
#define PHY_R16_ACKIE 0x4000 //Acknowledge Bit Received Interrupt Enable
#define PHY_R16_PRIE 0x2000 //Page Received INT Enable
#define PHY_R16_LCIE 0x1000 //Link Changed Enable
#define PHY_R16_ANIE 0x0800 //Auto-Negotiation Changed Enable
#define PHY_R16_PDFIE 0x0400 //Parallel Detect Fault Enable
#define PHY_R16_RFIE 0x0200 //Remote Fault Interrupt Enable
#define PHY_R16_JABIE 0x0100 //Jabber Interrupt Enable
#define PHY_R16_ACKR 0x0040 //Acknowledge Bit Received Interrupt Enable
#define PHY_R16_PGR 0x0020 //Page Received INT Enable
#define PHY_R16_LKC 0x0010 //Link Changed Enable
#define PHY_R16_ANC 0x0008 //Auto-Negotiation Changed Enable
#define PHY_R16_PDF 0x0004 //Parallel Detect Fault Enable
#define PHY_R16_RMTF 0x0002 //Remote Fault Interrupt Enable
#define PHY_R16_JABI 0x0001 //Jabber Interrupt Enable
////Proprietary Status Register
#define PHY_R17_LNK 0x4000 //
#define PHY_R17_DPM 0x2000 //Duplex Mode
#define PHY_R17_SPD 0x1000 //Speed
#define PHY_R17_ANNC 0x0400 //Auto-Negotiation Complete
#define PHY_R17_PRCVD 0x0200 //
#define PHY_R17_ANCM 0x0100 // Auto-Negotiation (A-N) Common Operating Mode
#define PHY_R17_PLR 0x0020 //
void EtherInit(void); //declare of some Init founctions
void init_addr(void);
/* Description : definition of EMAC FIFO buffer allocation*/
#define BUFA_FULL 99 /**<BUFA_FULL constant */
#define BUFB_FULL 66 /**<BUFB_FULL constant */
#define BUFMAP 4 /**<User select BUFMAP based on design to application buffer requirements */
#if BUFMAP > 4
#error Illegal FIFO buffer size
#endif
#if BUFMAP == 0
#define EMAC_RX_SZ 128 /**<BUFMAP == 0 */
#define EMAC_TX_SZ 128 /**<BUFMAP == 0 */
#elif BUFMAP == 1
#define EMAC_RX_SZ 256 /**<BUFMAP == 1 */
#define EMAC_TX_SZ 256 /**<BUFMAP == 1 */
#elif BUFMAP == 2
#define EMAC_RX_SZ 512 /**<BUFMAP == 2 */
#define EMAC_TX_SZ 512 /**<BUFMAP == 2 */
#elif BUFMAP == 3
#define EMAC_RX_SZ 1024 /**<BUFMAP == 3 */
#define EMAC_TX_SZ 1024 /**<BUFMAP == 3 */
#elif BUFMAP == 4
#define EMAC_RX_SZ 1536 /**<BUFMAP == 4 */
#define EMAC_TX_SZ 1536 /**<BUFMAP == 4 */
#endif
//uncomment to enable debug mode
//set ETH_DEBUG to 1 for detailed debug
//#define ETH_DEBUG 0
//#define ETH_DEBUG 1
void Debugt(tS08 *x);
void Debugi(tU16 x);
void Debugc(tU08 c);
void Debugnl(void);
void InitDebug(void);
#ifdef ETH_DEBUG
#define _INIT_DEBUG() InitDebug()
#define _DEBUGT(a) Debugt(a)
#define _DEBUGI(a) Debugi(a)
#define _DEBUGC(a) Debugc(a)
#define _DEBUGNL Debugnl()
#else
#define _INIT_DEBUG()
#define _DEBUGT(a)
#define _DEBUGI(a)
#define _DEBUGC(a)
#define _DEBUGNL
#endif
#endif
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