etherinit.c

MC9S12NE64串口与网络通信源代码

/*****************************************************************************
 *
 * File Name     : etherinit.c
 *
 * DESCRIPTION   : Low level initialization for EPHY and EMAC
 *
 * Description   : Ethernet Init
 *
 * Got from FREESCALE 
 * Modified by houlei @2004.10.10
 *****************************************************************************/

#include "MOTTYPES.h"
#include "etherinit.h"
#include "ne64api.h"
#include "ethernet.h"
#include "IO_Map.H"

extern eth_HwAddress sed_lclEthAddr;
extern in_HwAddress  sin_lclINAddr;
extern eth_HwAddress sed_ethBcastAddr;
extern tU32 myip;

extern tU16 gotxflowc;			/**<Global Variable For Determination of
                                      * Flow Control Packets are sent in Full Duplex
                                      * defined in "main.c" */

extern tU08	gotlink;            /**<Global Variable For Determination if
                                      * link is active (1=active)
                                      * defined in "main.c" */
                                      
void EtherInit()
{

  tU16 myctr; 								//generic counter variable
  tU16 mymrdata, mymwdata;                  //temp variable for MII read/write data
  tU16 angotduplex, 				    	//Auto negotiation control variable
       etypecontrol, 				        //Ethertype filter control variable
       addressfiltercontrol;	            //address filter control variable


  gotlink = 0;                              //No link present

  //=========================
  //PHY Inits	 - enable EPHY module	and EPHY Interrupt
  //=========================

  //Write PHY address before EPHYEN is set; this will latch EPHY register 14 on reset
  //address PHY 0 (default address of internal PHY); PHYADD0 | PHYADD1 | PHYADD2 | PHYADD3| PHYADD4
  EPHYCTL1 = PHY_ADDRESS;	 //Modify in "etherinit.h"

  //Enable EPHY module with PHY clocks disabled
  //Do not trun on PHY clocks untill both EMAC and EPHY are completely setup (see Below)
  EPHYCTL0 = EPHYCTL0_DIS100_MASK | EPHYCTL0_DIS10_MASK;
#if  AUTO_NEG
  //Enable auto_neg at start-up
  EPHYCTL0 = EPHYCTL0 & (~EPHYCTL0_ANDIS_MASK);
#else				//ELSE AUTO_NEG
  //Disable auto_neg at start-up
  EPHYCTL0 = EPHYCTL0 | EPHYCTL0_ANDIS_MASK;
#endif	    //AUTO_NEG

  //Enable EPHY module
  EPHYCTL0 = EPHYCTL0_EPHYEN_MASK | EPHYCTL0;      //Enable PHY

  //Enable EPHY LEDs and Interrupts
  EPHYCTL0 = EPHYCTL0 | (EPHYCTL0_LEDEN_MASK | EPHYCTL0_EPHYIEN_MASK );
 // while(!EPHYCTL0_LEDEN);                                             
  //DELAY, Delay staret-up
  for (myctr=0x18000; myctr >0; myctr--);                                            


  //=========================
  //EMAC Inits
  //========================

  //We do not duplex yet since auto_neg is not complete so use half as default
  angotduplex = 0; 				 //Auto negotiation control variable

  //Configure RX mode based on EtherInit() define settings
  addressfiltercontrol = 0;		 //address filter control variable
#if (BRODC_REJ)
    addressfiltercontrol = addressfiltercontrol | BCREJ;
#endif
#if (CON_MULTIC)
    addressfiltercontrol = addressfiltercontrol | CONMC;
#endif
#if (PROM_MODE)
    addressfiltercontrol = addressfiltercontrol | PROM;
#endif

  //Configure Ethertype based on EtherInit() define settings
  etypecontrol = 0;				 //Ethertype filter control variable
#if (ETYPE_PET)
    etypecontrol = etypecontrol | T_PET;
#endif
#if (ETYPE_EMW)
    etypecontrol = etypecontrol | T_EMW;
#endif
#if (ETYPE_IPV6)
    etypecontrol = etypecontrol | T_IPV6;
#endif
#if (ETYPE_ARP)
    etypecontrol = etypecontrol | T_ARP;
#endif
#if (ETYPE_IPV4)
    etypecontrol = etypecontrol | T_IPV4;
#endif
#if (ETYPE_IEEE)
    etypecontrol = etypecontrol | T_IEEE;
#endif
#if (ETYPE_ALL)
    etypecontrol = etypecontrol & T_ALL;
#endif

  //Initialize EMAC including MII management Interface
  EtherOpen(MII_MDCSEL(BUS_CLOCK),
            BUFMAP,                   // defined in 'emacfifocfg.h'
            RX_MAX_FL,                // RX max packet lenght
            (void *)sed_lclEthAddr,        // defined in 'address.h'
            etypecontrol,                // program ethertype fixed filter target */
            ETYPE_PRG,                // program prgramable ethertype value related to T_PET */
#if XFLOWC	        //this should be only enabled in auto negotiation if pause resolution confirms this (full duplex only)
            RFCE | addressfiltercontrol,
#else                       //ELSE XFLOWC
            addressfiltercontrol,
#endif						//XFLOWC

#if  AUTO_NEG
                                    //Configure Net Control: Duplex, external PHY, loopback, wait
            angotduplex		        //Half Duplex operation default until auto_neg is complete
#else			                   //ELSE AUTO_NEG (manual speed duplex settings)
#if FULL_DUPLEX
            NETCT_FDX               // full duplex operation */
#else                               //ELSE FULL_DUPLEX
            angotduplex             //Half Duplex operation */
#endif	                            //FULL_DUPLEX
#endif		                        //AUTO_NEG
            );

  //Enable Select EMAC interrrupt: 
  IMASK = IMASK_TXCIE_MASK | IMASK_ECIE_MASK | IMASK_LCIE_MASK;
#if (!RX_POLL_MODE)    //USE RX INTERRUPTS
  IMASK = IMASK | IMASK_RXACIE_MASK |  IMASK_RXBCIE_MASK;
#endif  // RX_POLL_MODE
  IMASK = IMASK | IMASK_RXAOIE_MASK|IMASK_RXBOIE_MASK | IMASK_RXEIE_MASK;				//Buffer Overruns & RX error
  IMASK = IMASK | IMASK_BREIE_MASK;             //Babbling Error		
  IMASK = IMASK | IMASK_RFCIE_MASK;				//RX flow Control								  


  //Transmit pause initialization: set bit and pause time  duration
#if XFLOWC

#if AUTO_NEG
//   EtherPause(1,PAUSE_TIME);			 // PAUSE_TIME defined in "etherinit.h"
#endif	  //AUTO_NEG

#if FULL_DUPLEX
   gotxflowc = 1;
//   EtherPause(1,PAUSE_TIME);
#endif	  //FULL_DUPLEX

#endif		//XFLOWC

//===============================================
// Configure PHY through EMAC MII Serial Management now that MII clock is set (address PHY is 0x00)
//===============================================
   //READ  PHY_REG_IDX: PHY idenfitication which is composed from OUI and make/model/revision of PHY
#if READ_PHY_ID
   //read PHY_REG_ID1
   while ( !(MIIread(PHY_ADDRESS, PHY_REG_ID1 , &mymrdata)) );

   //read PHY_REG_ID2 - should be:
   while ( !(MIIread(PHY_ADDRESS, PHY_REG_ID2 , &mymrdata))  );

   //read PHY_REG_ADDR - should be: 0x00
   while ( !(MIIread(PHY_ADDRESS, PHY_REG_ADDR , &mymrdata)) );
#endif


//Read PHY_REG_ANAR then configure the PHY Link abilities for auto_negoigation
#if AUTO_NEG
   while ( !(MIIread(PHY_ADDRESS, PHY_REG_ANAR, &mymrdata)) );

//Configure Flow Control PHY Link abilities advertisement
    mymwdata = mymrdata;
#if XFLOWC
   mymwdata = mymwdata | PHY_R4_FC;
#endif //#if XFLOWC

//Configure Speed and Duplex PHY Link abilities advertisement
#if (~HALF100 & 1)
    mymwdata = mymwdata & ~PHY_R4_100H;
#endif
#if (~HALF10  & 1)
    mymwdata = mymwdata & ~PHY_R4_10H;
#endif
#if (~FULL100  & 1)
    mymwdata = mymwdata & ~PHY_R4_100F;
#endif
#if (~FULL10  & 1)
    mymwdata = mymwdata & ~PHY_R4_10F;
#endif

   //Write PHY_REG_ANAR to configure PHY Link abilities advertisement
   while ( !(MIIwrite(PHY_ADDRESS, PHY_REG_ANAR, mymwdata  ))    );

#endif //#if AUTO_NEG

   //Enable PHY interrupts in Reg 16 (PHY Interrupt Control Register)
	 //Set PHY Interrupt Control Register
   mymwdata = PHY_R16_ACKIE | PHY_R16_PRIE | PHY_R16_LCIE | PHY_R16_ANIE;
   mymwdata = mymwdata | PHY_R16_PDFIE | PHY_R16_RFIE | PHY_R16_JABIE;

   
   while ( ! (MIIwrite(PHY_ADDRESS, PHY_REG_IR, mymwdata))   );                       

//===============================================
// Start up EPHY clocks (PLLs)
//===============================================

   //Read PHY Control Register 0
   while ( !(MIIread(PHY_ADDRESS, PHY_REG_CR, &mymrdata)) );


//Start up EPHY in auto negotiation
#if  AUTO_NEG

	 //Start PHY PLLs
     EPHYCTL0 = EPHYCTL0  & ~(EPHYCTL0_DIS100_MASK | EPHYCTL0_DIS10_MASK); //Let PHY PLLs be determined by PHY

//Start up EPHY without auto negotiation (CONFIGURE MANUALLY- SPEED AND DUPLEX)
#else	 //NO AUTO_NEG

//Set Duplex MANUALLY
#if FULL_DUPLEX
   mymwdata = mymrdata | PHY_R0_DPLX;		  //Set Full Duplex
#else                   //ELSE FULL_DUPLEX
   mymwdata = mymrdata & ~PHY_R0_DPLX;    //Set Half Duplex
#endif	                //FULL_DUPLEX

//Set Speed MANUALLY
#if SPEED100
   mymwdata = mymwdata | PHY_R0_DR;		//Set SPEED100
#else                   //ELSE SPEED100
   mymwdata = mymwdata & ~PHY_R0_DR;		//Set SPEED10
#endif	                //SPEED100

   //Write Config Register to set manually configure speed and duplex
   while ( !(MIIwrite(PHY_ADDRESS, PHY_REG_CR, mymwdata ))    );

	 //Start EPHY PLLs
   EPHYCTL0 = EPHYCTL0  & ~(EPHYCTL0_DIS100_MASK | EPHYCTL0_DIS10_MASK); //Let PHY PLLs be determined by PHY
    

#endif			      //AUTO_NEG

}

//***when used as a ethernet interface ,you have to config these****
//********
//******************************************************************
void init_addr(void){    

    sed_lclEthAddr[0]=0x12;
    sed_lclEthAddr[1]=0x34;
    sed_lclEthAddr[2]=0x56;
    sed_lclEthAddr[3]=0x78;
    sed_lclEthAddr[4]=0x9A;
    sed_lclEthAddr[5]=0xCC;
    
    sed_ethBcastAddr[0]=0xFF;
    sed_ethBcastAddr[1]=0xFF;
    sed_ethBcastAddr[2]=0xFF;
    sed_ethBcastAddr[3]=0xFF;
    sed_ethBcastAddr[4]=0xFF;
    sed_ethBcastAddr[5]=0xFF;
	
    sin_lclINAddr = myip;      //active when use changeip()

}