adn2.vhd

2位加法器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY adn2 IS
PORT( a,b:IN STD_LOGIC;
      q:OUT STD_LOGIC);
END adn2;
ARCHITECTURE be OF adn2 IS
 BEGIN  
 process(a,b)
  begin

     IF (a='1' and b='1') THEN 
           q<='1'; 
      else q<='0';
     end if;           
   END PROCESS;
END be;