prev_cmp_jtag_logic.fit.qmsg

特权制作的USB-Blaster全部相关资料

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_SLACK_TPD_RESULT" "register bitcount\[6\] register state\[1\] -8.267 ns " "Info: Slack time is -8.267 ns between source register \"bitcount\[6\]\" and destination register \"state\[1\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.291 ns + Largest register register " "Info: + Largest register to register requirement is 0.291 ns" {  } {  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.372 ns   Shortest register " "Info:   Shortest clock path from clock \"CLK\" to destination register is 3.372 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns CLK 1 CLK Unassigned 47 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = Unassigned; Fanout = 47; CLK Node = 'CLK'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.322 ns) + CELL(0.918 ns) 3.372 ns state\[1\] 2 REG Unassigned 21 " "Info: 2: + IC(1.322 ns) + CELL(0.918 ns) = 3.372 ns; Loc. = Unassigned; Fanout = 21; REG Node = 'state\[1\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.240 ns" { CLK state[1] } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 60.79 % ) " "Info: Total cell delay = 2.050 ns ( 60.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.322 ns ( 39.21 % ) " "Info: Total interconnect delay = 1.322 ns ( 39.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 9 -1 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.372 ns   Longest register " "Info:   Longest clock path from clock \"CLK\" to destination register is 3.372 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns CLK 1 CLK Unassigned 47 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = Unassigned; Fanout = 47; CLK Node = 'CLK'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.322 ns) + CELL(0.918 ns) 3.372 ns state\[1\] 2 REG Unassigned 21 " "Info: 2: + IC(1.322 ns) + CELL(0.918 ns) = 3.372 ns; Loc. = Unassigned; Fanout = 21; REG Node = 'state\[1\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.240 ns" { CLK state[1] } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 60.79 % ) " "Info: Total cell delay = 2.050 ns ( 60.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.322 ns ( 39.21 % ) " "Info: Total interconnect delay = 1.322 ns ( 39.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 9 -1 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.372 ns   Shortest register " "Info:   Shortest clock path from clock \"CLK\" to source register is 3.372 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns CLK 1 CLK Unassigned 47 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = Unassigned; Fanout = 47; CLK Node = 'CLK'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.322 ns) + CELL(0.918 ns) 3.372 ns bitcount\[6\] 2 REG Unassigned 4 " "Info: 2: + IC(1.322 ns) + CELL(0.918 ns) = 3.372 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'bitcount\[6\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.240 ns" { CLK bitcount[6] } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 60.79 % ) " "Info: Total cell delay = 2.050 ns ( 60.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.322 ns ( 39.21 % ) " "Info: Total interconnect delay = 1.322 ns ( 39.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 9 -1 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.372 ns   Longest register " "Info:   Longest clock path from clock \"CLK\" to source register is 3.372 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns CLK 1 CLK Unassigned 47 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = Unassigned; Fanout = 47; CLK Node = 'CLK'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.322 ns) + CELL(0.918 ns) 3.372 ns bitcount\[6\] 2 REG Unassigned 4 " "Info: 2: + IC(1.322 ns) + CELL(0.918 ns) = 3.372 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'bitcount\[6\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.240 ns" { CLK bitcount[6] } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 60.79 % ) " "Info: Total cell delay = 2.050 ns ( 60.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.322 ns ( 39.21 % ) " "Info: Total interconnect delay = 1.322 ns ( 39.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 9 -1 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns   " "Info:   Micro clock to output delay of source is 0.376 ns" {  } { { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 59 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns   " "Info:   Micro setup delay of destination is 0.333 ns" {  } { { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.558 ns - Longest register register " "Info: - Longest register to register delay is 8.558 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns bitcount\[6\] 1 REG Unassigned 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'bitcount\[6\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { bitcount[6] } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.251 ns) + CELL(0.200 ns) 2.451 ns Equal0~0 2 COMB Unassigned 2 " "Info: 2: + IC(2.251 ns) + CELL(0.200 ns) = 2.451 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'Equal0~0'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.451 ns" { bitcount[6] Equal0~0 } "NODE_NAME" } } { "c:/altera/90/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/90/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.200 ns) 3.631 ns Mux0~2 3 COMB Unassigned 1 " "Info: 3: + IC(0.980 ns) + CELL(0.200 ns) = 3.631 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'Mux0~2'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { Equal0~0 Mux0~2 } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.200 ns) 4.811 ns Mux0~3 4 COMB Unassigned 1 " "Info: 4: + IC(0.980 ns) + CELL(0.200 ns) = 4.811 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'Mux0~3'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { Mux0~2 Mux0~3 } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.440 ns) + CELL(0.740 ns) 5.991 ns Mux2~0 5 COMB Unassigned 1 " "Info: 5: + IC(0.440 ns) + CELL(0.740 ns) = 5.991 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'Mux2~0'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { Mux0~3 Mux2~0 } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.763 ns) + CELL(0.804 ns) 8.558 ns state\[1\] 6 REG Unassigned 21 " "Info: 6: + IC(1.763 ns) + CELL(0.804 ns) = 8.558 ns; Loc. = Unassigned; Fanout = 21; REG Node = 'state\[1\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.567 ns" { Mux2~0 state[1] } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.144 ns ( 25.05 % ) " "Info: Total cell delay = 2.144 ns ( 25.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.414 ns ( 74.95 % ) " "Info: Total interconnect delay = 6.414 ns ( 74.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "8.558 ns" { bitcount[6] Equal0~0 Mux0~2 Mux0~3 Mux2~0 state[1] } "NODE_NAME" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "8.558 ns" { bitcount[6] Equal0~0 Mux0~2 Mux0~3 Mux2~0 state[1] } "NODE_NAME" } }  } 0 0 "Slack time is %5!s! between source %1!s! \"%2!s!\" and destination %3!s! \"%4!s!\"" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "8.558 ns register register " "Info: Estimated most critical path is register to register delay of 8.558 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns bitcount\[6\] 1 REG LAB_X5_Y1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X5_Y1; Fanout = 4; REG Node = 'bitcount\[6\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { bitcount[6] } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.251 ns) + CELL(0.200 ns) 2.451 ns Equal0~0 2 COMB LAB_X5_Y2 2 " "Info: 2: + IC(2.251 ns) + CELL(0.200 ns) = 2.451 ns; Loc. = LAB_X5_Y2; Fanout = 2; COMB Node = 'Equal0~0'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.451 ns" { bitcount[6] Equal0~0 } "NODE_NAME" } } { "c:/altera/90/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/90/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.200 ns) 3.631 ns Mux0~2 3 COMB LAB_X5_Y2 1 " "Info: 3: + IC(0.980 ns) + CELL(0.200 ns) = 3.631 ns; Loc. = LAB_X5_Y2; Fanout = 1; COMB Node = 'Mux0~2'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { Equal0~0 Mux0~2 } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.200 ns) 4.811 ns Mux0~3 4 COMB LAB_X5_Y2 1 " "Info: 4: + IC(0.980 ns) + CELL(0.200 ns) = 4.811 ns; Loc. = LAB_X5_Y2; Fanout = 1; COMB Node = 'Mux0~3'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { Mux0~2 Mux0~3 } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.440 ns) + CELL(0.740 ns) 5.991 ns Mux2~0 5 COMB LAB_X5_Y2 1 " "Info: 5: + IC(0.440 ns) + CELL(0.740 ns) = 5.991 ns; Loc. = LAB_X5_Y2; Fanout = 1; COMB Node = 'Mux2~0'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { Mux0~3 Mux2~0 } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.763 ns) + CELL(0.804 ns) 8.558 ns state\[1\] 6 REG LAB_X6_Y3 21 " "Info: 6: + IC(1.763 ns) + CELL(0.804 ns) = 8.558 ns; Loc. = LAB_X6_Y3; Fanout = 21; REG Node = 'state\[1\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.567 ns" { Mux2~0 state[1] } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.144 ns ( 25.05 % ) " "Info: Total cell delay = 2.144 ns ( 25.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.414 ns ( 74.95 % ) " "Info: Total interconnect delay = 6.414 ns ( 74.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "8.558 ns" { bitcount[6] Equal0~0 Mux0~2 Mux0~3 Mux2~0 state[1] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "11 " "Info: Average interconnect usage is 11% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "11 X0_Y0 X8_Y5 " "Info: Peak interconnect usage is 11% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IFIOMGR_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "D\[0\]~en " "Info: Following pins have the same output enable: D\[0\]~en" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bi-directional D\[0\] 3.3-V LVTTL " "Info: Type bi-directional pin D\[0\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { D[0] } } } { "c:/altera/90/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90/quartus/bin/Assignment Editor.qase" 1 { { 0 "D\[0\]" } } } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[0] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0 -1}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "D\[2\]~en " "Info: Following pins have the same output enable: D\[2\]~en" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bi-directional D\[2\] 3.3-V LVTTL " "Info: Type bi-directional pin D\[2\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { D[2] } } } { "c:/altera/90/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90/quartus/bin/Assignment Editor.qase" 1 { { 0 "D\[2\]" } } } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[2] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0 -1} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bi-directional D\[4\] 3.3-V LVTTL " "Info: Type bi-directional pin D\[4\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { D[4] } } } { "c:/altera/90/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90/quartus/bin/Assignment Editor.qase" 1 { { 0 "D\[4\]" } } } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[4] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0 -1} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bi-directional D\[6\] 3.3-V LVTTL " "Info: Type bi-directional pin D\[6\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { D[6] } } } { "c:/altera/90/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90/quartus/bin/Assignment Editor.qase" 1 { { 0 "D\[6\]" } } } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[6] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0 -1} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bi-directional D\[1\] 3.3-V LVTTL " "Info: Type bi-directional pin D\[1\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { D[1] } } } { "c:/altera/90/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90/quartus/bin/Assignment Editor.qase" 1 { { 0 "D\[1\]" } } } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[1] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0 -1} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bi-directional D\[3\] 3.3-V LVTTL " "Info: Type bi-directional pin D\[3\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { D[3] } } } { "c:/altera/90/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90/quartus/bin/Assignment Editor.qase" 1 { { 0 "D\[3\]" } } } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[3] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0 -1} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bi-directional D\[5\] 3.3-V LVTTL " "Info: Type bi-directional pin D\[5\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { D[5] } } } { "c:/altera/90/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90/quartus/bin/Assignment Editor.qase" 1 { { 0 "D\[5\]" } } } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[5] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0 -1} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bi-directional D\[7\] 3.3-V LVTTL " "Info: Type bi-directional pin D\[7\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { D[7] } } } { "c:/altera/90/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90/quartus/bin/Assignment Editor.qase" 1 { { 0 "D\[7\]" } } } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[7] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0 -1}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Following groups of pins have the same output enable" 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.fit.smsg " "Info: Generated suppressed messages file E:/xjwjj/USB blaster/verilog_prj/jtag_logic.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "192 " "Info: Peak virtual memory: 192 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 02 09:01:29 2009 " "Info: Processing ended: Wed Sep 02 09:01:29 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}