prev_cmp_jtag_logic.fit.qmsg

特权制作的USB-Blaster全部相关资料

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 02 09:01:25 2009 " "Info: Processing started: Wed Sep 02 09:01:25 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off jtag_logic -c jtag_logic " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off jtag_logic -c jtag_logic" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "IMPP_MPP_USER_DEVICE" "jtag_logic EPM240T100C5 " "Info: Selected device EPM240T100C5 for design \"jtag_logic\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Info: Device EPM240T100I5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Info: Device EPM240T100A5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Info: Device EPM570T100C5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Info: Device EPM570T100I5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Info: Device EPM570T100A5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "4 21 " "Warning: No exact pin location assignment(s) for 4 pins of 21 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B_NCE " "Info: Pin B_NCE not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { B_NCE } } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 16 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { B_NCE } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B_NCS " "Info: Pin B_NCS not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { B_NCS } } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 17 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { B_NCS } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B_OE " "Info: Pin B_OE not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { B_OE } } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 19 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { B_OE } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B_ASDO " "Info: Pin B_ASDO not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { B_ASDO } } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 13 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { B_ASDO } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0 -1} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tsu 2.0 ns " "Info: Assuming a global tsu requirement of 2.0 ns" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0 -1} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tco 1.0 ns " "Info: Assuming a global tco requirement of 1.0 ns" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0 -1} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tpd 1.0 ns " "Info: Assuming a global tpd requirement of 1.0 ns" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}