prev_cmp_jtag_logic.qmsg

特权制作的USB-Blaster全部相关资料

{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "7.888 ns register register " "Info: Estimated most critical path is register to register delay of 7.888 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns bitcount\[6\] 1 REG LAB_X3_Y4 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X3_Y4; Fanout = 4; REG Node = 'bitcount\[6\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { bitcount[6] } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/Personal/USB blaster/verilog_prj/jtag_logic.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.557 ns) + CELL(0.200 ns) 1.757 ns Equal0~49 2 COMB LAB_X2_Y4 2 " "Info: 2: + IC(1.557 ns) + CELL(0.200 ns) = 1.757 ns; Loc. = LAB_X2_Y4; Fanout = 2; COMB Node = 'Equal0~49'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.757 ns" { bitcount[6] Equal0~49 } "NODE_NAME" } } { "d:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.200 ns) 2.937 ns Mux0~969 3 COMB LAB_X2_Y4 1 " "Info: 3: + IC(0.980 ns) + CELL(0.200 ns) = 2.937 ns; Loc. = LAB_X2_Y4; Fanout = 1; COMB Node = 'Mux0~969'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { Equal0~49 Mux0~969 } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/Personal/USB blaster/verilog_prj/jtag_logic.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.200 ns) 4.117 ns Mux0~970 4 COMB LAB_X2_Y4 1 " "Info: 4: + IC(0.980 ns) + CELL(0.200 ns) = 4.117 ns; Loc. = LAB_X2_Y4; Fanout = 1; COMB Node = 'Mux0~970'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { Mux0~969 Mux0~970 } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/Personal/USB blaster/verilog_prj/jtag_logic.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.440 ns) + CELL(0.740 ns) 5.297 ns Mux2~19 5 COMB LAB_X2_Y4 1 " "Info: 5: + IC(0.440 ns) + CELL(0.740 ns) = 5.297 ns; Loc. = LAB_X2_Y4; Fanout = 1; COMB Node = 'Mux2~19'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { Mux0~970 Mux2~19 } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/Personal/USB blaster/verilog_prj/jtag_logic.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.787 ns) + CELL(0.804 ns) 7.888 ns state\[1\] 6 REG LAB_X2_Y3 20 " "Info: 6: + IC(1.787 ns) + CELL(0.804 ns) = 7.888 ns; Loc. = LAB_X2_Y3; Fanout = 20; REG Node = 'state\[1\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.591 ns" { Mux2~19 state[1] } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/Personal/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.144 ns ( 27.18 % ) " "Info: Total cell delay = 2.144 ns ( 27.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.744 ns ( 72.82 % ) " "Info: Total interconnect delay = 5.744 ns ( 72.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.888 ns" { bitcount[6] Equal0~49 Mux0~969 Mux0~970 Mux2~19 state[1] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "11 " "Info: Average interconnect usage is 11% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "11 X0_Y0 X8_Y5 " "Info: Peak interconnect usage is 11% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 0}
{ "Info" "IFIOMGR_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "D\[0\]~en " "Info: Following pins have the same output enable: D\[0\]~en" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bi-directional D\[0\] 3.3-V LVTTL " "Info: Type bi-directional pin D\[0\] uses the 3.3-V LVTTL I/O standard" {  } { { "d:/altera/81/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/81/quartus/bin/pin_planner.ppl" { D[0] } } } { "jtag_logic.vhd" "" { Text "E:/Personal/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[0] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bi-directional D\[2\] 3.3-V LVTTL " "Info: Type bi-directional pin D\[2\] uses the 3.3-V LVTTL I/O standard" {  } { { "d:/altera/81/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/81/quartus/bin/pin_planner.ppl" { D[2] } } } { "jtag_logic.vhd" "" { Text "E:/Personal/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[2] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bi-directional D\[4\] 3.3-V LVTTL " "Info: Type bi-directional pin D\[4\] uses the 3.3-V LVTTL I/O standard" {  } { { "d:/altera/81/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/81/quartus/bin/pin_planner.ppl" { D[4] } } } { "jtag_logic.vhd" "" { Text "E:/Personal/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[4] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bi-directional D\[6\] 3.3-V LVTTL " "Info: Type bi-directional pin D\[6\] uses the 3.3-V LVTTL I/O standard" {  } { { "d:/altera/81/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/81/quartus/bin/pin_planner.ppl" { D[6] } } } { "jtag_logic.vhd" "" { Text "E:/Personal/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[6] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bi-directional D\[1\] 3.3-V LVTTL " "Info: Type bi-directional pin D\[1\] uses the 3.3-V LVTTL I/O standard" {  } { { "d:/altera/81/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/81/quartus/bin/pin_planner.ppl" { D[1] } } } { "jtag_logic.vhd" "" { Text "E:/Personal/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[1] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bi-directional D\[3\] 3.3-V LVTTL " "Info: Type bi-directional pin D\[3\] uses the 3.3-V LVTTL I/O standard" {  } { { "d:/altera/81/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/81/quartus/bin/pin_planner.ppl" { D[3] } } } { "jtag_logic.vhd" "" { Text "E:/Personal/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[3] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bi-directional D\[5\] 3.3-V LVTTL " "Info: Type bi-directional pin D\[5\] uses the 3.3-V LVTTL I/O standard" {  } { { "d:/altera/81/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/81/quartus/bin/pin_planner.ppl" { D[5] } } } { "jtag_logic.vhd" "" { Text "E:/Personal/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[5] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bi-directional D\[7\] 3.3-V LVTTL " "Info: Type bi-directional pin D\[7\] uses the 3.3-V LVTTL I/O standard" {  } { { "d:/altera/81/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/81/quartus/bin/pin_planner.ppl" { D[7] } } } { "jtag_logic.vhd" "" { Text "E:/Personal/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[7] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0 "" 0 0}  } {  } 0 0 "Following groups of pins have the same output enable" 0 0 "" 0 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/Personal/USB blaster/verilog_prj/jtag_logic.fit.smsg " "Info: Generated suppressed messages file E:/Personal/USB blaster/verilog_prj/jtag_logic.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 0}
{ "Info" "IQCU_PARALLEL_USED" "1.0 2 2 " "Info: Parallel compilation was enabled and used an average of 1.0 processors and a maximum of 2 processors out of 2 processors allowed" { { "Info" "IQCU_PARALLEL_INSIGNIFICANT_TIME" "" "Info: Less than 1% of process time was spent using more than one processor" {  } {  } 0 0 "Less than 1%% of process time was spent using more than one processor" 0 0 "" 0 0}  } {  } 0 0 "Parallel compilation was enabled and used an average of %1!s! processors and a maximum of %2!i! processors out of %3!i! processors allowed" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "184 " "Info: Peak virtual memory: 184 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 04 19:45:21 2009 " "Info: Processing ended: Mon May 04 19:45:21 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Info: Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Full Version " "Info: Version 8.1 Build 163 10/28/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 04 19:45:23 2009 " "Info: Processing started: Mon May 04 19:45:23 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off jtag_logic -c jtag_logic " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off jtag_logic -c jtag_logic" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}