jtag_logic.fit.rpt

特权制作的USB-Blaster全部相关资料

+--------------------------------------------------------------------+
; Fitter Device Options                                              ;
+----------------------------------------------+---------------------+
; Option                                       ; Setting             ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                 ;
; Enable device-wide reset (DEV_CLRn)          ; Off                 ;
; Enable device-wide output enable (DEV_OE)    ; Off                 ;
; Enable INIT_DONE output                      ; Off                 ;
; Configuration scheme                         ; Passive Serial      ;
; Reserve all unused pins                      ; As input tri-stated ;
; Base pin-out file on sameframe device        ; Off                 ;
+----------------------------------------------+---------------------+


+------------------------------------------------------------+
; Estimated Delay Added for Hold Timing                      ;
+-----------------+----------------------+-------------------+
; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
+-----------------+----------------------+-------------------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Status Code        ; 0     ;
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+----------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                        ;
+--------------------------------------------------------------------------------+-------------+
; Name                                                                           ; Value       ;
+--------------------------------------------------------------------------------+-------------+
; Auto Fit Point 1 - Fit Attempt 1                                               ; ff          ;
; Mid Wire Use - Fit Attempt 1                                                   ; 21          ;
; Mid Slack - Fit Attempt 1                                                      ; -9611       ;
; Internal Atom Count - Fit Attempt 1                                            ; 75          ;
; LE/ALM Count - Fit Attempt 1                                                   ; 75          ;
; LAB Count - Fit Attempt 1                                                      ; 11          ;
; Outputs per Lab - Fit Attempt 1                                                ; 5.545       ;
; Inputs per LAB - Fit Attempt 1                                                 ; 7.273       ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 0.909       ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:11        ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:7;1:3;2:1 ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:7;1:3;2:1 ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:7;1:3;2:1 ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:7;1:3;2:1 ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:7;1:3;2:1 ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:11        ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:11        ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:7;1:3;2:1 ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:1;1:10    ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:1;1:7;2:3 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:11        ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:1;1:10    ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:9;1:2     ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:5;1:6     ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:11        ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:11        ;
; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1                    ; 1:11        ;
; LEs in Chains - Fit Attempt 1                                                  ; 9           ;
; LEs in Long Chains - Fit Attempt 1                                             ; 0           ;
; LABs with Chains - Fit Attempt 1                                               ; 1           ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0           ;
; Time - Fit Attempt 1                                                           ; 0           ;
; Time in tsm_tan.dll - Fit Attempt 1                                            ; 0.016       ;
+--------------------------------------------------------------------------------+-------------+


+----------------------------------------------+
; Advanced Data - Placement                    ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Auto Fit Point 2 - Fit Attempt 1    ; ff     ;
; Early Wire Use - Fit Attempt 1      ; 5      ;
; Early Slack - Fit Attempt 1         ; -10154 ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff     ;
; Mid Wire Use - Fit Attempt 1        ; 12     ;
; Mid Slack - Fit Attempt 1           ; -8921  ;
; Auto Fit Point 6 - Fit Attempt 1    ; ff     ;
; Auto Fit Point 6 - Fit Attempt 1    ; ff     ;
; Auto Fit Point 6 - Fit Attempt 1    ; ff     ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff     ;
; Mid Wire Use - Fit Attempt 1        ; 12     ;
; Mid Slack - Fit Attempt 1           ; -8921  ;
; Auto Fit Point 6 - Fit Attempt 1    ; ff     ;
; Auto Fit Point 6 - Fit Attempt 1    ; ff     ;
; Auto Fit Point 6 - Fit Attempt 1    ; ff     ;
; Late Wire Use - Fit Attempt 1       ; 14     ;
; Late Slack - Fit Attempt 1          ; -8921  ;
; Peak Regional Wire - Fit Attempt 1  ; 0.000  ;
; Auto Fit Point 7 - Fit Attempt 1    ; ff     ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.047  ;
+-------------------------------------+--------+


+---------------------------------------------------+
; Advanced Data - Routing                           ;
+-------------------------------------+-------------+
; Name                                ; Value       ;
+-------------------------------------+-------------+
; Early Slack - Fit Attempt 1         ; -8268       ;
; Early Wire Use - Fit Attempt 1      ; 14          ;
; Peak Regional Wire - Fit Attempt 1  ; 13          ;
; Mid Slack - Fit Attempt 1           ; -8338       ;
; Late Slack - Fit Attempt 1          ; -2147483648 ;
; Late Wire Use - Fit Attempt 1       ; 15          ;
; Time - Fit Attempt 1                ; 0           ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016       ;
+-------------------------------------+-------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
    Info: Processing started: Wed Sep 02 10:17:29 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off jtag_logic -c jtag_logic
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Selected device EPM240T100C5 for design "jtag_logic"
Info: Low junction temperature is 0 degrees C
Info: High junction temperature is 85 degrees C
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM240T100A5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
    Info: Device EPM570T100A5 is compatible
Warning: No exact pin location assignment(s) for 1 pins of 21 total pins
    Info: Pin B_OE not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "CLK" to use Global clock in PI