jtag_logic.map.rpt

特权制作的USB-Blaster全部相关资料

; Synthesis Effort                                               ; Auto               ; Auto               ;
; Allows Asynchronous Clear Usage For Shift Register Replacement ; On                 ; On                 ;
; Analysis & Synthesis Message Level                             ; Medium             ; Medium             ;
+----------------------------------------------------------------+--------------------+--------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                             ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                                                ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------+
; jtag_logic.vhd                   ; yes             ; User VHDL File  ; E:/xjwjj/USB blaster/SF-USBblaster V2.0 (090902)/verilog_prj/jtag_logic.vhd ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 77    ;
;     -- Combinational with no register       ; 30    ;
;     -- Register only                        ; 20    ;
;     -- Combinational with a register        ; 27    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 32    ;
;     -- 3 input functions                    ; 14    ;
;     -- 2 input functions                    ; 10    ;
;     -- 1 input functions                    ; 1     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 69    ;
;     -- arithmetic mode                      ; 8     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 9     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 47    ;
; Total logic cells in carry chains           ; 9     ;
; I/O pins                                    ; 21    ;
; Maximum fan-out node                        ; CLK   ;
; Maximum fan-out                             ; 47    ;
; Total fan-out                               ; 318   ;
; Average fan-out                             ; 3.24  ;
+---------------------------------------------+-------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                  ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |jtag_logic                ; 77 (77)     ; 47           ; 0          ; 21   ; 0            ; 30 (30)      ; 20 (20)           ; 27 (27)          ; 9 (9)           ; 0 (0)      ; |jtag_logic         ; work         ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 47    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 9     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 21    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |jtag_logic|bitcount[2]    ;
; 3:1                ; 6 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |jtag_logic|bitcount[3]    ;
; 4:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; Yes        ; |jtag_logic|ioshifter[2]   ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |jtag_logic|ioshifter[0]   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
    Info: Processing started: Wed Sep 02 10:17:22 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jtag_logic -c jtag_logic
Info: Found 2 design units, including 1 entities, in source file jtag_logic.vhd
    Info: Found design unit 1: jtag_logic-behavior
    Info: Found entity 1: jtag_logic
Info: Elaborating entity "jtag_logic" for the top level hierarchy
Info: Implemented 98 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 8 output pins
    Info: Implemented 8 bidirectional pins
    Info: Implemented 77 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 193 megabytes
    Info: Processing ended: Wed Sep 02 10:17:27 2009
    Info: Elapsed time: 00:00:05
    Info: Total CPU time (on all processors): 00:00:02