dds.tan.rpt

经过仿真验证的

; Clock Setup: 'CLK'           ; N/A   ; None          ; 290.87 MHz ( period = 3.438 ns ) ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a0~porta_address_reg9 ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[0] ; CLK        ; CLK      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                                                                                                           ;                                                                                  ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1S10F484C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                                                                                                         ;
+-------+------------------------------------------------+-----------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                                                                                      ; To                                                                                                        ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-----------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 290.87 MHz ( period = 3.438 ns )               ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a3~porta_address_reg0 ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[6]                          ; CLK        ; CLK      ; None                        ; None                      ; 2.875 ns                ;
; N/A   ; 290.87 MHz ( period = 3.438 ns )               ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a3~porta_address_reg1 ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[6]                          ; CLK        ; CLK      ; None                        ; None                      ; 2.875 ns                ;
; N/A   ; 290.87 MHz ( period = 3.438 ns )               ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a3~porta_address_reg2 ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[6]                          ; CLK        ; CLK      ; None                        ; None                      ; 2.875 ns                ;