📄 display.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY display IS
PORT( clk: IN STD_LOGIC;--时钟信号
light: in integer range 1 to 6;--电梯的位置
segout: OUT STD_LOGIC_VECTOR(6 downto 0));--数码管显示
end;
ARCHITECTURE behave OF display IS
signal dp:std_logic_vector(6 downto 0);
begin
process(clk)
begin
if(clk'event and clk='1')then
case light is
when 1 =>
dp<="0000110";--显示1
when 2 =>
dp<="1011011";--显示2
when 3 =>
dp<="1001111";--显示3
when 4 =>
dp<="0110011";--显示4
when 5 =>
dp<="1011011";--显示5
when 6 =>
dp<="1011111";--显示6
when others =>
dp<="0000000";
end case;
end if;
end process;
segout<=dp;
end;
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