prev_cmp_lift.qmsg

不同于网上的四层电梯

{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/f6lift/lift.fit.smsg " "Info: Generated suppressed messages file D:/f6lift/lift.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "235 " "Info: Allocated 235 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 04 12:50:44 2008 " "Info: Processing ended: Wed Jun 04 12:50:44 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 04 12:50:45 2008 " "Info: Processing started: Wed Jun 04 12:50:45 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off lift -c lift " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off lift -c lift" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "188 " "Info: Allocated 188 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 04 12:50:58 2008 " "Info: Processing ended: Wed Jun 04 12:50:58 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 04 12:50:59 2008 " "Info: Processing started: Wed Jun 04 12:50:59 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off lift -c lift --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off lift -c lift --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "buttonclk " "Info: Assuming node \"buttonclk\" is an undefined clock" {  } { { "lift.vhd" "" { Text "D:/f6lift/lift.vhd" 7 -1 0 } } { "f:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "buttonclk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "liftclk " "Info: Assuming node \"liftclk\" is an undefined clock" {  } { { "lift.vhd" "" { Text "D:/f6lift/lift.vhd" 8 -1 0 } } { "f:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "liftclk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "buttonclk register register fuplight\[5\]~reg0 fuplight\[5\]~reg0 420.17 MHz Internal " "Info: Clock \"buttonclk\" Internal fmax is restricted to 420.17 MHz between source register \"fuplight\[5\]~reg0\" and destination register \"fuplight\[5\]~reg0\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.961 ns + Longest register register " "Info: + Longest register to register delay is 0.961 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fuplight\[5\]~reg0 1 REG LCFF_X63_Y21_N27 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X63_Y21_N27; Fanout = 5; REG Node = 'fuplight\[5\]~reg0'" {  } { { "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { fuplight[5]~reg0 } "NODE_NAME" } } { "lift.vhd" "" { Text "D:/f6lift/lift.vhd" 319 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.324 ns) + CELL(0.150 ns) 0.474 ns fuplight~904 2 COMB LCCOMB_X63_Y21_N2 1 " "Info: 2: + IC(0.324 ns) + CELL(0.150 ns) = 0.474 ns; Loc. = LCCOMB_X63_Y21_N2; Fanout = 1; COMB Node = 'fuplight~904'" {  } { { "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.474 ns" { fuplight[5]~reg0 fuplight~904 } "NODE_NAME" } } { "lift.vhd" "" { Text "D:/f6lift/lift.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.254 ns) + CELL(0.149 ns) 0.877 ns fuplight~905 3 COMB LCCOMB_X63_Y21_N26 1 " "Info: 3: + IC(0.254 ns) + CELL(0.149 ns) = 0.877 ns; Loc. = LCCOMB_X63_Y21_N26; Fanout = 1; COMB Node = 'fuplight~905'" {  } { { "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.403 ns" { fuplight~904 fuplight~905 } "NODE_NAME" } } { "lift.vhd" "" { Text "D:/f6lift/lift.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.961 ns fuplight\[5\]~reg0 4 REG LCFF_X63_Y21_N27 5 " "Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 0.961 ns; Loc. = LCFF_X63_Y21_N27; Fanout = 5; REG Node = 'fuplight\[5\]~reg0'" {  } { { "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { fuplight~905 fuplight[5]~reg0 } "NODE_NAME" } } { "lift.vhd" "" { Text "D:/f6lift/lift.vhd" 319 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.383 ns ( 39.85 % ) " "Info: Total cell delay = 0.383 ns ( 39.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.578 ns ( 60.15 % ) " "Info: Total interconnect delay = 0.578 ns ( 60.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.961 ns" { fuplight[5]~reg0 fuplight~904 fuplight~905 fuplight[5]~reg0 } "NODE_NAME" } } { "f:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.961 ns" { fuplight[5]~reg0 fuplight~904 fuplight~905 fuplight[5]~reg0 } { 0.000ns 0.324ns 0.254ns 0.000ns } { 0.000ns 0.150ns 0.149ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "buttonclk destination 2.680 ns + Shortest register " "Info: + Shortest clock path from clock \"buttonclk\" to destination register is 2.680 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns buttonclk 1 CLK PIN_P1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P1; Fanout = 1; CLK Node = 'buttonclk'" {  } { { "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { buttonclk } "NODE_NAME" } } { "lift.vhd" "" { Text "D:/f6lift/lift.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.112 ns buttonclk~clkctrl 2 COMB CLKCTRL_G3 21 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G3; Fanout = 21; COMB Node = 'buttonclk~clkctrl'" {  } { { "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.113 ns" { buttonclk buttonclk~clkctrl } "NODE_NAME" } } { "lift.vhd" "" { Text "D:/f6lift/lift.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.537 ns) 2.680 ns fuplight\[5\]~reg0 3 REG LCFF_X63_Y21_N27 5 " "Info: 3: + IC(1.031 ns) + CELL(0.537 ns) = 2.680 ns; Loc. = LCFF_X63_Y21_N27; Fanout = 5; REG Node = 'fuplight\[5\]~reg0'" {  } { { "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.568 ns" { buttonclk~clkctrl fuplight[5]~reg0 } "NODE_NAME" } } { "lift.vhd" "" { Text "D:/f6lift/lift.vhd" 319 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.31 % ) " "Info: Total cell delay = 1.536 ns ( 57.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.144 ns ( 42.69 % ) " "Info: Total interconnect delay = 1.144 ns ( 42.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.680 ns" { buttonclk buttonclk~clkctrl fuplight[5]~reg0 } "NODE_NAME" } } { "f:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.680 ns" { buttonclk buttonclk~combout buttonclk~clkctrl fuplight[5]~reg0 } { 0.000ns 0.000ns 0.113ns 1.031ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "buttonclk source 2.680 ns - Longest register " "Info: - Longest clock path from clock \"buttonclk\" to source register is 2.680 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns buttonclk 1 CLK PIN_P1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P1; Fanout = 1; CLK Node = 'buttonclk'" {  } { { "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { buttonclk } "NODE_NAME" } } { "lift.vhd" "" { Text "D:/f6lift/lift.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.112 ns buttonclk~clkctrl 2 COMB CLKCTRL_G3 21 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G3; Fanout = 21; COMB Node = 'buttonclk~clkctrl'" {  } { { "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.113 ns" { buttonclk buttonclk~clkctrl } "NODE_NAME" } } { "lift.vhd" "" { Text "D:/f6lift/lift.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.537 ns) 2.680 ns fuplight\[5\]~reg0 3 REG LCFF_X63_Y21_N27 5 " "Info: 3: + IC(1.031 ns) + CELL(0.537 ns) = 2.680 ns; Loc. = LCFF_X63_Y21_N27; Fanout = 5; REG Node = 'fuplight\[5\]~reg0'" {  } { { "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.568 ns" { buttonclk~clkctrl fuplight[5]~reg0 } "NODE_NAME" } } { "lift.vhd" "" { Text "D:/f6lift/lift.vhd" 319 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.31 % ) " "Info: Total cell delay = 1.536 ns ( 57.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.144 ns ( 42.69 % ) " "Info: Total interconnect delay = 1.144 ns ( 42.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.680 ns" { buttonclk buttonclk~clkctrl fuplight[5]~reg0 } "NODE_NAME" } } { "f:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.680 ns" { buttonclk buttonclk~combout buttonclk~clkctrl fuplight[5]~reg0 } { 0.000ns 0.000ns 0.113ns 1.031ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.680 ns" { buttonclk buttonclk~clkctrl fuplight[5]~reg0 } "NODE_NAME" } } { "f:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.680 ns" { buttonclk buttonclk~combout buttonclk~clkctrl fuplight[5]~reg0 } { 0.000ns 0.000ns 0.113ns 1.031ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.680 ns" { buttonclk buttonclk~clkctrl fuplight[5]~reg0 } "NODE_NAME" } } { "f:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.680 ns" { buttonclk buttonclk~combout buttonclk~clkctrl fuplight[5]~reg0 } { 0.000ns 0.000ns 0.113ns 1.031ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "lift.vhd" "" { Text "D:/f6lift/lift.vhd" 319 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "lift.vhd" "" { Text "D:/f6lift/lift.vhd" 319 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.961 ns" { fuplight[5]~reg0 fuplight~904 fuplight~905 fuplight[5]~reg0 } "NODE_NAME" } } { "f:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.961 ns" { fuplight[5]~reg0 fuplight~904 fuplight~905 fuplight[5]~reg0 } { 0.000ns 0.324ns 0.254ns 0.000ns } { 0.