rs232_txd_source_code.txt

RS232 Transmitter VHDL Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Rs232Txd is
port( Reset, Send, Clock16x: in std_logic;
DataIn: in std_logic_vector(7 downto 0);
Txd: out std_logic);
end Rs232Txd;
architecture Rs232Txd_Arch of Rs232Txd is
attribute enum_encoding: string;
-- state definitions
type stateType is (stIdle, stData, stStop, stTxdCompleted);
attribute enum_encoding of stateType: type is "00 01 11 10";
signal presState: stateType;
signal nextState: stateType;
signal iSend, iReset, iClock1xEnable, iEnableTxdBuffer, iEnableShift:
std_logic;
signal iTxdBuffer: std_logic_vector (9 downto 0);
signal iClockDiv: std_logic_vector (3 downto 0);
signal iClock1x: std_logic;
signal iNoBitsSent: std_logic_vector (3 downto 0);
begin
process (Clock16x)
begin
if Clock16x'event and Clock16x = '1' then
if Reset = '1' or iReset = '1' then
iSend <= '0';
iEnableTxdBuffer <= '0';
iEnableShift <= '0';
iClock1xEnable <= '0';
iClockDiv <= (others=>'0');

end if;
if Send = '1' or iSend = '1' then
iClock1xEnable <= '1';
end if;
if iClock1xEnable = '1' then
iClockDiv <= iClockDiv + '1';
end if;

if iEnableTxdBuffer = '1' then
iTxdBuffer <= '1' & DataIn & '0'; -- inserting start bit and stop bit
end if;
end if;
end process;
iClock1x <= iClockDiv(3);
process (iClock1xEnable, iClock1x)
begin
if iClock1xEnable = '0' then
iNoBitsSent <= (others=>'0');
presState <= stIdle;
elsif iClock1x'event and iClock1x = '1' then
iNoBitsSent <= iNoBitsSent + '1';
presState <= nextState;
end if;
if iClock1x'event and iClock1x = '1' then

if iEnableShift = '1' then
iTxdBuffer <= '0' & iTxdBuffer(9 downto 1);
end if;
end if;
end process;
Txd <= iTxdBuffer(0);
process (presState, iClock1xEnable, iNoBitsSent)
begin
-- signal defaults
iReset <= '0';
iEnableTxdBuffer <= '0';
iEnableShift <= '0';
case presState is
when stIdle =>
if iClock1xEnable = '1' then
iEnableTxdBuffer <= '1';
nextState <= stData;
else
nextState <= stIdle;
end if;
when stData =>
i
if iNoBitsSent = "1010" then
iEnableShift <= '0';
nextState <= stStop;
else
iEnableShift <= '1';
nextState <= stData;
end if;
when stStop =>
nextState <= stTxdCompleted;
when stTxdCompleted =>
iReset <= '1';
nextState <= stIdle;
end case;
end process;

end Rs232Txd_Arch;