prev_cmp_test.map.qmsg

vhdl 电子钟 计时 上下午 整点报时

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jan 03 19:37:06 2009 " "Info: Processing started: Sat Jan 03 19:37:06 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off test -c test " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test -c test" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file clock.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "clock.bdf" "" { Schematic "G:/quartus/test/clock.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mincount60.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mincount60.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mincount60-behave " "Info: Found design unit 1: mincount60-behave" {  } { { "mincount60.vhd" "" { Text "G:/quartus/test/mincount60.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 mincount60 " "Info: Found entity 1: mincount60" {  } { { "mincount60.vhd" "" { Text "G:/quartus/test/mincount60.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fz500Hz.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fz500Hz.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fz500Hz-behav " "Info: Found design unit 1: fz500Hz-behav" {  } { { "fz500Hz.vhd" "" { Text "G:/quartus/test/fz500Hz.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 fz500Hz " "Info: Found entity 1: fz500Hz" {  } { { "fz500Hz.vhd" "" { Text "G:/quartus/test/fz500Hz.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div1000.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file div1000.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div1000-behav " "Info: Found design unit 1: div1000-behav" {  } { { "div1000.vhd" "" { Text "G:/quartus/test/div1000.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 div1000 " "Info: Found entity 1: div1000" {  } { { "div1000.vhd" "" { Text "G:/quartus/test/div1000.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "key_scan.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file key_scan.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 key_scan-behave " "Info: Found design unit 1: key_scan-behave" {  } { { "key_scan.vhd" "" { Text "G:/quartus/test/key_scan.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 key_scan " "Info: Found entity 1: key_scan" {  } { { "key_scan.vhd" "" { Text "G:/quartus/test/key_scan.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "key_scan " "Info: Elaborating entity \"key_scan\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "col key_scan.vhd(19) " "Warning (10492): VHDL Process Statement warning at key_scan.vhd(19): signal \"col\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "key_scan.vhd" "" { Text "G:/quartus/test/key_scan.vhd" 19 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "row\[0\] GND " "Warning: Pin \"row\[0\]\" stuck at GND" {  } { { "key_scan.vhd" "" { Text "G:/quartus/test/key_scan.vhd" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "row\[1\] VCC " "Warning: Pin \"row\[1\]\" stuck at VCC" {  } { { "key_scan.vhd" "" { Text "G:/quartus/test/key_scan.vhd" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "row\[2\] VCC " "Warning: Pin \"row\[2\]\" stuck at VCC" {  } { { "key_scan.vhd" "" { Text "G:/quartus/test/key_scan.vhd" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "row\[3\] VCC " "Warning: Pin \"row\[3\]\" stuck at VCC" {  } { { "key_scan.vhd" "" { Text "G:/quartus/test/key_scan.vhd" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "clk " "Warning: No output dependent on input pin \"clk\"" {  } { { "key_scan.vhd" "" { Text "G:/quartus/test/key_scan.vhd" 8 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "19 " "Info: Implemented 19 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "7 " "Info: Implemented 7 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_MCELLS" "7 " "Info: Implemented 7 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "145 " "Info: Allocated 145 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Jan 03 19:37:13 2009 " "Info: Processing ended: Sat Jan 03 19:37:13 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}