📄 top.map.rpt
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+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 19 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 11 ;
; Number of registers using Asynchronous Clear ; 4 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-----------------------------------------------------+
; Source assignments for Speaker1:u2 ;
+----------------+-------+------+---------------------+
; Assignment ; Value ; From ; To ;
+----------------+-------+------+---------------------+
; POWER_UP_LEVEL ; Low ; - ; GenSpkS:Count11[0] ;
; POWER_UP_LEVEL ; Low ; - ; GenSpkS:Count11[1] ;
; POWER_UP_LEVEL ; Low ; - ; GenSpkS:Count11[2] ;
; POWER_UP_LEVEL ; Low ; - ; GenSpkS:Count11[3] ;
; POWER_UP_LEVEL ; Low ; - ; GenSpkS:Count11[4] ;
; POWER_UP_LEVEL ; Low ; - ; GenSpkS:Count11[5] ;
; POWER_UP_LEVEL ; Low ; - ; GenSpkS:Count11[6] ;
; POWER_UP_LEVEL ; Low ; - ; GenSpkS:Count11[7] ;
; POWER_UP_LEVEL ; Low ; - ; GenSpkS:Count11[8] ;
; POWER_UP_LEVEL ; Low ; - ; GenSpkS:Count11[9] ;
; POWER_UP_LEVEL ; Low ; - ; GenSpkS:Count11[10] ;
; POWER_UP_LEVEL ; Low ; - ; DivideCLK:Count4[0] ;
; POWER_UP_LEVEL ; Low ; - ; DivideCLK:Count4[1] ;
; POWER_UP_LEVEL ; Low ; - ; DivideCLK:Count4[2] ;
; POWER_UP_LEVEL ; Low ; - ; DivideCLK:Count4[3] ;
+----------------+-------+------+---------------------+
+----------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: Speaker1:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0 ;
+------------------------+-------------------+-------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------------+-------------------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 11 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ;
; DEVICE_FAMILY ; ACEX1K ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+-------------------+-------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-----------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: Speaker1:u2|lpm_counter:\DivideCLK:Count4[0]_rtl_1 ;
+------------------------+-------------------+--------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------------+--------------------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 4 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ;
; DEVICE_FAMILY ; ACEX1K ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+-------------------+--------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Tue Nov 04 20:21:24 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off TOP -c TOP
Info: Found 2 design units, including 1 entities, in source file music_freq.vhd
Info: Found design unit 1: MUSIC_FREQ-a
Info: Found entity 1: MUSIC_FREQ
Info: Found 2 design units, including 1 entities, in source file organ.vhd
Info: Found design unit 1: ORGAN-A
Info: Found entity 1: ORGAN
Info: Found 2 design units, including 1 entities, in source file speaker.vhd
Info: Found design unit 1: Speaker-one
Info: Found entity 1: Speaker
Info: Found 2 design units, including 1 entities, in source file TONE.VHD
Info: Found design unit 1: Tone-one
Info: Found entity 1: Tone
Info: Found 2 design units, including 1 entities, in source file TOP.VHD
Info: Found design unit 1: TOP-one
Info: Found entity 1: TOP
Info: Found 2 design units, including 1 entities, in source file speaker1.vhd
Info: Found design unit 1: Speaker1-one
Info: Found entity 1: Speaker1
Info: Elaborating entity "TOP" for the top level hierarchy
Info: Elaborating entity "Tone" for hierarchy "Tone:u1"
Warning (10492): VHDL Process Statement warning at TONE.VHD(19): signal "KLK" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at TONE.VHD(23): signal "KLK" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at TONE.VHD(34): signal "KLK" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at TONE.VHD(45): signal "KLK" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "Speaker1" for hierarchy "Speaker1:u2"
Info: Inferred 2 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=11) from the following logic: "Speaker1:u2|\GenSpkS:Count11[0]~0"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "Speaker1:u2|\DivideCLK:Count4[0]~0"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Elaborated megafunction instantiation "Speaker1:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf
Info: Found entity 1: alt_counter_f10ke
Info: Elaborated megafunction instantiation "Speaker1:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter", which is child of megafunction instantiation "Speaker1:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0"
Info: Instantiated megafunction "Speaker1:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0" with the following parameter:
Info: Parameter "LPM_WIDTH" = "11"
Info: Parameter "LPM_DIRECTION" = "UP"
Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Info: Elaborated megafunction instantiation "Speaker1:u2|lpm_counter:\DivideCLK:Count4[0]_rtl_1"
Info: Elaborated megafunction instantiation "Speaker1:u2|lpm_counter:\DivideCLK:Count4[0]_rtl_1|alt_counter_f10ke:wysi_counter", which is child of megafunction instantiation "Speaker1:u2|lpm_counter:\DivideCLK:Count4[0]_rtl_1"
Info: Instantiated megafunction "Speaker1:u2|lpm_counter:\DivideCLK:Count4[0]_rtl_1" with the following parameter:
Info: Parameter "LPM_WIDTH" = "4"
Info: Parameter "LPM_DIRECTION" = "UP"
Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Info: Duplicate registers merged to single register
Info: Duplicate register "Speaker1:u2|\DelaySpkS:Count2" merged to single register "Speaker1:u2|SpkS"
Warning: Output pins are stuck at VCC or GND
Warning: Pin "CODE1[3]" stuck at GND
Warning: Pin "NUME1[2]" stuck at GND
Warning: Pin "NUME1[3]" stuck at GND
Warning: Pin "IO_DS[1]" stuck at VCC
Warning: Pin "IO_DS[2]" stuck at GND
Warning: Pin "IO_DS[3]" stuck at GND
Warning: Pin "IO_DS[4]" stuck at VCC
Warning: Pin "IO_DS[5]" stuck at GND
Warning: Pin "IO_DS[6]" stuck at GND
Info: Implemented 144 device resources after synthesis - the final resource count might be different
Info: Implemented 9 input pins
Info: Implemented 16 output pins
Info: Implemented 119 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 14 warnings
Info: Processing ended: Tue Nov 04 20:21:48 2008
Info: Elapsed time: 00:00:25
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