top.tan.qmsg

利用VHDL编写的电子琴发生器

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "Speaker:u2\|lpm_counter:\\DivideCLK:Count4\[0\]_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[2\] " "Info: Detected ripple clock \"Speaker:u2\|lpm_counter:\\DivideCLK:Count4\[0\]_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[2\]\" as buffer" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Speaker:u2\|lpm_counter:\\DivideCLK:Count4\[0\]_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "Speaker:u2\|lpm_counter:\\DivideCLK:Count4\[0\]_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\] " "Info: Detected ripple clock \"Speaker:u2\|lpm_counter:\\DivideCLK:Count4\[0\]_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\]\" as buffer" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Speaker:u2\|lpm_counter:\\DivideCLK:Count4\[0\]_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Speaker:u2\|LessThan~24 " "Info: Detected gated clock \"Speaker:u2\|LessThan~24\" as buffer" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Speaker:u2\|LessThan~24" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "Speaker:u2\|FullSpkS " "Info: Detected ripple clock \"Speaker:u2\|FullSpkS\" as buffer" {  } { { "Top.vhd" "" { Text "d:/我的文档/桌面/zhanglei/top/Top.vhd" 116 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Speaker:u2\|FullSpkS" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "HORL1 register register Tone:u1\|KLK\[1\] Tone:u1\|KLK\[1\] 200.0 MHz Internal " "Info: Clock \"HORL1\" Internal fmax is restricted to 200.0 MHz between source register \"Tone:u1\|KLK\[1\]\" and destination register \"Tone:u1\|KLK\[1\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.300 ns + Longest register register " "Info: + Longest register to register delay is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Tone:u1\|KLK\[1\] 1 REG LC1_E5 24 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_E5; Fanout = 24; REG Node = 'Tone:u1\|KLK\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "" { Tone:u1|KLK[1] } "NODE_NAME" } "" } } { "Top.vhd" "" { Text "d:/我的文档/桌面/zhanglei/top/Top.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.000 ns) 1.300 ns Tone:u1\|KLK\[1\] 2 REG LC1_E5 24 " "Info: 2: + IC(0.300 ns) + CELL(1.000 ns) = 1.300 ns; Loc. = LC1_E5; Fanout = 24; REG Node = 'Tone:u1\|KLK\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "1.300 ns" { Tone:u1|KLK[1] Tone:u1|KLK[1] } "NODE_NAME" } "" } } { "Top.vhd" "" { Text "d:/我的文档/桌面/zhanglei/top/Top.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.000 ns ( 76.92 % ) " "Info: Total cell delay = 1.000 ns ( 76.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns ( 23.08 % ) " "Info: Total interconnect delay = 0.300 ns ( 23.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "1.300 ns" { Tone:u1|KLK[1] Tone:u1|KLK[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.300 ns" { Tone:u1|KLK[1] Tone:u1|KLK[1] } { 0.000ns 0.300ns } { 0.000ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "HORL1 destination 2.400 ns + Shortest register " "Info: + Shortest clock path from clock \"HORL1\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns HORL1 1 CLK PIN_183 2 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_183; Fanout = 2; CLK Node = 'HORL1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "" { HORL1 } "NODE_NAME" } "" } } { "Top.vhd" "" { Text "d:/我的文档/桌面/zhanglei/top/Top.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns Tone:u1\|KLK\[1\] 2 REG LC1_E5 24 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_E5; Fanout = 24; REG Node = 'Tone:u1\|KLK\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "0.400 ns" { HORL1 Tone:u1|KLK[1] } "NODE_NAME" } "" } } { "Top.vhd" "" { Text "d:/我的文档/桌面/zhanglei/top/Top.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "2.400 ns" { HORL1 Tone:u1|KLK[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.400 ns" { HORL1 HORL1~out Tone:u1|KLK[1] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "HORL1 source 2.400 ns - Longest register " "Info: - Longest clock path from clock \"HORL1\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns HORL1 1 CLK PIN_183 2 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_183; Fanout = 2; CLK Node = 'HORL1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "" { HORL1 } "NODE_NAME" } "" } } { "Top.vhd" "" { Text "d:/我的文档/桌面/zhanglei/top/Top.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns Tone:u1\|KLK\[1\] 2 REG LC1_E5 24 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_E5; Fanout = 24; REG Node = 'Tone:u1\|KLK\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "0.400 ns" { HORL1 Tone:u1|KLK[1] } "NODE_NAME" } "" } } { "Top.vhd" "" { Text "d:/我的文档/桌面/zhanglei/top/Top.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "2.400 ns" { HORL1 Tone:u1|KLK[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.400 ns" { HORL1 HORL1~out Tone:u1|KLK[1] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "2.400 ns" { HORL1 Tone:u1|KLK[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.400 ns" { HORL1 HORL1~out Tone:u1|KLK[1] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "2.400 ns" { HORL1 Tone:u1|KLK[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.400 ns" { HORL1 HORL1~out Tone:u1|KLK[1] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "Top.vhd" "" { Text "d:/我的文档/桌面/zhanglei/top/Top.vhd" 52 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "Top.vhd" "" { Text "d:/我的文档/桌面/zhanglei/top/Top.vhd" 52 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "1.300 ns" { Tone:u1|KLK[1] Tone:u1|KLK[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.300 ns" { Tone:u1|KLK[1] Tone:u1|KLK[1] } { 0.000ns 0.300ns } { 0.000ns 1.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "2.400 ns" { HORL1 Tone:u1|KLK[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.400 ns" { HORL1 HORL1~out Tone:u1|KLK[1] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "2.400 ns" { HORL1 Tone:u1|KLK[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.400 ns" { HORL1 HORL1~out Tone:u1|KLK[1] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "" { Tone:u1|KLK[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { Tone:u1|KLK[1] } {  } {  } } } { "Top.vhd" "" { Text "d:/我的文档/桌面/zhanglei/top/Top.vhd" 52 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK12MHZ register Speaker:u2\|lpm_counter:\\GenSpkS:Count11\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[5\] register Speaker:u2\|lpm_counter:\\GenSpkS:Count11\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[10\] 87.72 MHz 11.4 ns Internal " "Info: Clock \"CLK12MHZ\" has Internal fmax of 87.72 MHz between source register \"Speaker:u2\|lpm_counter:\\GenSpkS:Count11\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[5\]\" and destination register \"Speaker:u2\|lpm_counter:\\GenSpkS:Count11\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[10\]\" (period= 11.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.100 ns + Longest register register " "Info: + Longest register to register delay is 10.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Speaker:u2\|lpm_counter:\\GenSpkS:Count11\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[5\] 1 REG LC1_E3 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_E3; Fanout = 3; REG Node = 'Speaker:u2\|lpm_counter:\\GenSpkS:Count11\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[5\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "" { Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.600 ns) 2.500 ns rtl~84 2 COMB LC1_E1 1 " "Info: 2: + IC(0.900 ns) + CELL(1.600 ns) = 2.500 ns; Loc. = LC1_E1; Fanout = 1; COMB Node = 'rtl~84'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "2.500 ns" { Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] rtl~84 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.800 ns) 4.300 ns rtl~92 3 COMB LC7_E3 1 " "Info: 3: + IC(1.000 ns) + CELL(0.800 ns) = 4.300 ns; Loc. = LC7_E3; Fanout = 1; COMB Node = 'rtl~92'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "1.800 ns" { rtl~84 rtl~92 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 5.900 ns rtl~87 4 COMB LC8_E3 2 " "Info: 4: + IC(0.000 ns) + CELL(1.600 ns) = 5.900 ns; Loc. = LC8_E3; Fanout = 2; COMB Node = 'rtl~87'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "1.600 ns" { rtl~92 rtl~87 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.400 ns) 8.300 ns rtl~89 5 COMB LC2_E1 13 " "Info: 5: + IC(1.000 ns) + CELL(1.400 ns) = 8.300 ns; Loc. = LC2_E1; Fanout = 13; COMB Node = 'rtl~89'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "2.400 ns" { rtl~87 rtl~89 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.800 ns) 10.100 ns Speaker:u2\|lpm_counter:\\GenSpkS:Count11\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[10\] 6 REG LC6_E3 2 " "Info: 6: + IC(1.000 ns) + CELL(0.800 ns) = 10.100 ns; Loc. = LC6_E3; Fanout = 2; REG Node = 'Speaker:u2\|lpm_counter:\\GenSpkS:Count11\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[10\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "1.800 ns" { rtl~89 Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[10] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.200 ns ( 61.39 % ) " "Info: Total cell delay = 6.200 ns ( 61.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.900 ns ( 38.61 % ) " "Info: Total interconnect delay = 3.900 ns ( 38.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "10.100 ns" { Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] rtl~84 rtl~92 rtl~87 rtl~89 Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[10] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.100 ns" { Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] rtl~84 rtl~92 rtl~87 rtl~89 Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[10] } { 0.000ns 0.900ns 1.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.600ns 0.800ns 1.600ns 1.400ns 0.800ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.200 ns - Smallest " "Info: - Smallest clock skew is -0.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK12MHZ destination 7.200 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK12MHZ\" to destination register is 7.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK12MHZ 1 CLK PIN_79 5 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_79; Fanout = 5; CLK Node = 'CLK12MHZ'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "" { CLK12MHZ } "NODE_NAME" } "" } } { "Top.vhd" "" { Text "d:/我的文档/桌面/zhanglei/top/Top.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns Speaker:u2\|lpm_counter:\\DivideCLK:Count4\[0\]_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC6_D2 2 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC6_D2; Fanout = 2; REG Node = 'Speaker:u2\|lpm_counter:\\DivideCLK:Count4\[0\]_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "0.900 ns" { CLK12MHZ Speaker:u2|lpm_counter:\DivideCLK:Count4[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 4.600 ns Speaker:u2\|LessThan~24 3 COMB LC1_D2 19 " "Info: 3: + IC(0.300 ns) + CELL(1.400 ns) = 4.600 ns; Loc. = LC1_D2; Fanout = 19; COMB Node = 'Speaker:u2\|LessThan~24'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "1.700 ns" { Speaker:u2|lpm_counter:\DivideCLK:Count4[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[3] Speaker:u2|LessThan~24 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(0.000 ns) 7.200 ns Speaker:u2\|lpm_counter:\\GenSpkS:Count11\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[10\] 4 REG LC6_E3 2 " "Info: 4: + IC(2.600 ns) + CELL(0.000 ns) = 7.200 ns; Loc. = LC6_E3; Fanout = 2; REG Node = 'Speaker:u2\|lpm_counter:\\GenSpkS:Count11\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[10\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "2.600 ns" { Speaker:u2|LessThan~24 Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[10] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns ( 54.17 % ) " "Info: Total cell delay = 3.900 ns ( 54.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns ( 45.83 % ) " "Info: Total interconnect delay = 3.300 ns ( 45.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "7.200 ns" { CLK12MHZ Speaker:u2|lpm_counter:\DivideCLK:Count4[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[3] Speaker:u2|LessThan~24 Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[10] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.200 ns" { CLK12MHZ CLK12MHZ~out Speaker:u2|lpm_counter:\DivideCLK:Count4[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[3] Speaker:u2|LessThan~24 Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[10] } { 0.000ns 0.000ns 0.400ns 0.300ns 2.600ns } { 0.000ns 2.000ns 0.500ns 1.400ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK12MHZ source 7.400 ns - Longest register " "Info: - Longest clock path from clock \"CLK12MHZ\" to source register is 7.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK12MHZ 1 CLK PIN_79 5 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_79; Fanout = 5; CLK Node = 'CLK12MHZ'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "" { CLK12MHZ } "NODE_NAME" } "" } } { "Top.vhd" "" { Text "d:/我的文档/桌面/zhanglei/top/Top.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns Speaker:u2\|lpm_counter:\\DivideCLK:Count4\[0\]_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[2\] 2 REG LC5_D2 4 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC5_D2; Fanout = 4; REG Node = 'Speaker:u2\|lpm_counter:\\DivideCLK:Count4\[0\]_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "0.900 ns" { CLK12MHZ Speaker:u2|lpm_counter:\DivideCLK:Count4[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 4.800 ns Speaker:u2\|LessThan~24 3 COMB LC1_D2 19 " "Info: 3: + IC(0.300 ns) + CELL(1.600 ns) = 4.800 ns; Loc. = LC1_D2; Fanout = 19; COMB Node = 'Speaker:u2\|LessThan~24'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "1.900 ns" { Speaker:u2|lpm_counter:\DivideCLK:Count4[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[2] Speaker:u2|LessThan~24 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(0.000 ns) 7.400 ns Speaker:u2\|lpm_counter:\\GenSpkS:Count11\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[5\] 4 REG LC1_E3 3 " "Info: 4: + IC(2.600 ns) + CELL(0.000 ns) = 7.400 ns; Loc. = LC1_E3; Fanout = 3; REG Node = 'Speaker:u2\|lpm_counter:\\GenSpkS:Count11\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[5\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "2.600 ns" { Speaker:u2|LessThan~24 Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.100 ns ( 55.41 % ) " "Info: Total cell delay = 4.100 ns ( 55.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns ( 44.59 % ) " "Info: Total interconnect delay = 3.300 ns ( 44.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "7.400 ns" { CLK12MHZ Speaker:u2|lpm_counter:\DivideCLK:Count4[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[2] Speaker:u2|LessThan~24 Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.400 ns" { CLK12MHZ CLK12MHZ~out Speaker:u2|lpm_counter:\DivideCLK:Count4[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[2] Speaker:u2|LessThan~24 Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } { 0.000ns 0.000ns 0.400ns 0.300ns 2.600ns } { 0.000ns 2.000ns 0.500ns 1.600ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "7.200 ns" { CLK12MHZ Speaker:u2|lpm_counter:\DivideCLK:Count4[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[3] Speaker:u2|LessThan~24 Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[10] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.200 ns" { CLK12MHZ CLK12MHZ~out Speaker:u2|lpm_counter:\DivideCLK:Count4[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[3] Speaker:u2|LessThan~24 Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[10] } { 0.000ns 0.000ns 0.400ns 0.300ns 2.600ns } { 0.000ns 2.000ns 0.500ns 1.400ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "7.400 ns" { CLK12MHZ Speaker:u2|lpm_counter:\DivideCLK:Count4[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[2] Speaker:u2|LessThan~24 Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.400 ns" { CLK12MHZ CLK12MHZ~out Speaker:u2|lpm_counter:\DivideCLK:Count4[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[2] Speaker:u2|LessThan~24 Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } { 0.000ns 0.000ns 0.400ns 0.300ns 2.600ns } { 0.000ns 2.000ns 0.500ns 1.600ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "10.100 ns" { Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] rtl~84 rtl~92 rtl~87 rtl~89 Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[10] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.100 ns" { Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] rtl~84 rtl~92 rtl~87 rtl~89 Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[10] } { 0.000ns 0.900ns 1.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.600ns 0.800ns 1.600ns 1.400ns 0.800ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "7.200 ns" { CLK12MHZ Speaker:u2|lpm_counter:\DivideCLK:Count4[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[3] Speaker:u2|LessThan~24 Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[10] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.200 ns" { CLK12MHZ CLK12MHZ~out Speaker:u2|lpm_counter:\DivideCLK:Count4[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[3] Speaker:u2|LessThan~24 Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[10] } { 0.000ns 0.000ns 0.400ns 0.300ns 2.600ns } { 0.000ns 2.000ns 0.500ns 1.400ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Top" "UNKNOWN" "V1" "d:/我的文档/桌面/zhanglei/top/db/Top.quartus_db" { Floorplan "d:/我的文档/桌面/zhanglei/top/" "" "7.400 ns" { CLK12MHZ Speaker:u2|lpm_counter:\DivideCLK:Count4[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[2] Speaker:u2|LessThan~24 Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.400 ns" { CLK12MHZ CLK12MHZ~out Speaker:u2|lpm_counter:\DivideCLK:Count4[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[2] Speaker:u2|LessThan~24 Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } { 0.000ns 0.000ns 0.400ns 0.300ns 2.600ns } { 0.000ns 2.000ns 0.500ns 1.600ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}