top.map.qmsg

利用VHDL编写的电子琴发生器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Nov 08 19:18:43 2008 " "Info: Processing started: Sat Nov 08 19:18:43 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Top -c Top " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Top -c Top" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Top.vhd 6 3 " "Info: Found 6 design units, including 3 entities, in source file Top.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 TOP-one " "Info: Found design unit 1: TOP-one" {  } { { "Top.vhd" "" { Text "d:/我的文档/桌面/zhanglei/top/Top.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 Tone-one " "Info: Found design unit 2: Tone-one" {  } { { "Top.vhd" "" { Text "d:/我的文档/桌面/zhanglei/top/Top.vhd" 47 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 Speaker-one " "Info: Found design unit 3: Speaker-one" {  } { { "Top.vhd" "" { Text "d:/我的文档/桌面/zhanglei/top/Top.vhd" 115 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 TOP " "Info: Found entity 1: TOP" {  } { { "Top.vhd" "" { Text "d:/我的文档/桌面/zhanglei/top/Top.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 Tone " "Info: Found entity 2: Tone" {  } { { "Top.vhd" "" { Text "d:/我的文档/桌面/zhanglei/top/Top.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 Speaker " "Info: Found entity 3: Speaker" {  } { { "Top.vhd" "" { Text "d:/我的文档/桌面/zhanglei/top/Top.vhd" 110 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Top " "Info: Elaborating entity \"Top\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Tone Tone:u1 " "Info: Elaborating entity \"Tone\" for hierarchy \"Tone:u1\"" {  } { { "Top.vhd" "u1" { Text "d:/我的文档/桌面/zhanglei/top/Top.vhd" 27 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "KLK Top.vhd(54) " "Warning (10492): VHDL Process Statement warning at Top.vhd(54): signal \"KLK\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Top.vhd" "" { Text "d:/我的文档/桌面/zhanglei/top/Top.vhd" 54 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "KLK Top.vhd(58) " "Warning (10492): VHDL Process Statement warning at Top.vhd(58): signal \"KLK\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Top.vhd" "" { Text "d:/我的文档/桌面/zhanglei/top/Top.vhd" 58 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "KLK Top.vhd(69) " "Warning (10492): VHDL Process Statement warning at Top.vhd(69): signal \"KLK\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Top.vhd" "" { Text "d:/我的文档/桌面/zhanglei/top/Top.vhd" 69 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "KLK Top.vhd(80) " "Warning (10492): VHDL Process Statement warning at Top.vhd(80): signal \"KLK\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Top.vhd" "" { Text "d:/我的文档/桌面/zhanglei/top/Top.vhd" 80 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Speaker Speaker:u2 " "Info: Elaborating entity \"Speaker\" for hierarchy \"Speaker:u2\"" {  } { { "Top.vhd" "u2" { Text "d:/我的文档/桌面/zhanglei/top/Top.vhd" 29 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Speaker:u2\|\\GenSpkS:Count11\[0\]~0 11 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=11) from the following logic: \"Speaker:u2\|\\GenSpkS:Count11\[0\]~0\"" {  } {  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "Speaker:u2\|\\DivideCLK:Count4\[0\]~0 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Speaker:u2\|\\DivideCLK:Count4\[0\]~0\"" {  } {  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 250 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "Speaker:u2\|\\DelaySpkS:Count2 Speaker:u2\|SpkS " "Info: Duplicate register \"Speaker:u2\|\\DelaySpkS:Count2\" merged to single register \"Speaker:u2\|SpkS\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "CODE1\[3\] GND " "Warning: Pin \"CODE1\[3\]\" stuck at GND" {  } { { "Top.vhd" "" { Text "d:/我的文档/桌面/zhanglei/top/Top.vhd" 6 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "NUME1\[2\] GND " "Warning: Pin \"NUME1\[2\]\" stuck at GND" {  } { { "Top.vhd" "" { Text "d:/我的文档/桌面/zhanglei/top/Top.vhd" 8 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "NUME1\[3\] GND " "Warning: Pin \"NUME1\[3\]\" stuck at GND" {  } { { "Top.vhd" "" { Text "d:/我的文档/桌面/zhanglei/top/Top.vhd" 8 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "138 " "Info: Implemented 138 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "9 " "Info: Implemented 9 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "119 " "Info: Implemented 119 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Nov 08 19:18:51 2008 " "Info: Processing ended: Sat Nov 08 19:18:51 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}