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利用VHDL编写的电子琴发生器

+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1K30QC208-3      ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; HORL1           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; CLK12MHZ        ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'HORL1'                                                                                                                                                                                 ;
+-------+------------------------------------------------+----------------+----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From           ; To             ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+----------------+----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; Tone:u1|KLK[1] ; Tone:u1|KLK[1] ; HORL1      ; HORL1    ; None                        ; None                      ; 1.300 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; Tone:u1|KLK[0] ; Tone:u1|KLK[1] ; HORL1      ; HORL1    ; None                        ; None                      ; 1.100 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; Tone:u1|KLK[0] ; Tone:u1|KLK[0] ; HORL1      ; HORL1    ; None                        ; None                      ; 1.100 ns                ;
+-------+------------------------------------------------+----------------+----------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK12MHZ'                                                                                                                                                                                                                                                                                                                            ;
+-------+------------------------------------------------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                                                                  ; To                                                                                    ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 87.72 MHz ( period = 11.400 ns )               ; Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; CLK12MHZ   ; CLK12MHZ ; None                        ; None                      ; 10.100 ns               ;
; N/A   ; 87.72 MHz ( period = 11.400 ns )               ; Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; CLK12MHZ   ; CLK12MHZ ; None                        ; None                      ; 10.100 ns               ;
; N/A   ; 87.72 MHz ( period = 11.400 ns )               ; Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; CLK12MHZ   ; CLK12MHZ ; None                        ; None                      ; 10.100 ns               ;