top.tan.rpt

来自「利用VHDL编写的电子琴发生器」· RPT 代码 · 共 274 行 · 第 1/5 页

Timing Analyzer report for Top
Sat Nov 08 19:19:14 2008
Version 5.1 Build 176 10/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'HORL1'
  6. Clock Setup: 'CLK12MHZ'
  7. tsu
  8. tco
  9. tpd
 10. th
 11. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                    ;
+------------------------------+-------+---------------+------------------------------------------------+--------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From                                                                                 ; To                                                                                   ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+--------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 15.600 ns                                      ; INDEX1[2]                                                                            ; Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; --         ; CLK12MHZ ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 17.200 ns                                      ; Speaker:u2|SpkS                                                                      ; SPKOUT                                                                               ; CLK12MHZ   ; --       ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 19.800 ns                                      ; INDEX1[5]                                                                            ; CODE1[1]                                                                             ; --         ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -4.500 ns                                      ; INDEX1[5]                                                                            ; Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[8] ; --         ; CLK12MHZ ; 0            ;
; Clock Setup: 'CLK12MHZ'      ; N/A   ; None          ; 87.72 MHz ( period = 11.400 ns )               ; Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; Speaker:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; CLK12MHZ   ; CLK12MHZ ; 0            ;
; Clock Setup: 'HORL1'         ; N/A   ; None          ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; Tone:u1|KLK[1]                                                                       ; Tone:u1|KLK[1]                                                                       ; HORL1      ; HORL1    ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;                                                                                      ;                                                                                      ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+--------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------+------------+----------+--------------+