top.map.qmsg

利用VHDL编写的电子琴发生器

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Tone Tone:u1 " "Info: Elaborating entity \"Tone\" for hierarchy \"Tone:u1\"" {  } { { "TOP.VHD" "u1" { Text "d:/我的文档/桌面/zhanglei/整合/TOP.VHD" 30 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "KLK TONE.VHD(19) " "Warning (10492): VHDL Process Statement warning at TONE.VHD(19): signal \"KLK\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "TONE.VHD" "" { Text "d:/我的文档/桌面/zhanglei/整合/TONE.VHD" 19 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "KLK TONE.VHD(23) " "Warning (10492): VHDL Process Statement warning at TONE.VHD(23): signal \"KLK\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "TONE.VHD" "" { Text "d:/我的文档/桌面/zhanglei/整合/TONE.VHD" 23 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "KLK TONE.VHD(35) " "Warning (10492): VHDL Process Statement warning at TONE.VHD(35): signal \"KLK\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "TONE.VHD" "" { Text "d:/我的文档/桌面/zhanglei/整合/TONE.VHD" 35 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "KLK TONE.VHD(47) " "Warning (10492): VHDL Process Statement warning at TONE.VHD(47): signal \"KLK\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "TONE.VHD" "" { Text "d:/我的文档/桌面/zhanglei/整合/TONE.VHD" 47 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Speaker1 Speaker1:u2 " "Info: Elaborating entity \"Speaker1\" for hierarchy \"Speaker1:u2\"" {  } { { "TOP.VHD" "u2" { Text "d:/我的文档/桌面/zhanglei/整合/TOP.VHD" 32 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Speaker1:u2\|\\GenSpkS:Count11\[0\]~0 11 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=11) from the following logic: \"Speaker1:u2\|\\GenSpkS:Count11\[0\]~0\"" {  } {  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "Speaker1:u2\|\\DivideCLK:Count4\[0\]~0 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Speaker1:u2\|\\DivideCLK:Count4\[0\]~0\"" {  } {  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 250 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "Speaker1:u2\|\\DelaySpkS:Count2 Speaker1:u2\|SpkS " "Info: Duplicate register \"Speaker1:u2\|\\DelaySpkS:Count2\" merged to single register \"Speaker1:u2\|SpkS\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "NUME1\[2\] GND " "Warning: Pin \"NUME1\[2\]\" stuck at GND" {  } { { "TOP.VHD" "" { Text "d:/我的文档/桌面/zhanglei/整合/TOP.VHD" 8 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "NUME1\[3\] GND " "Warning: Pin \"NUME1\[3\]\" stuck at GND" {  } { { "TOP.VHD" "" { Text "d:/我的文档/桌面/zhanglei/整合/TOP.VHD" 8 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "IO_DS\[1\] VCC " "Warning: Pin \"IO_DS\[1\]\" stuck at VCC" {  } { { "TOP.VHD" "" { Text "d:/我的文档/桌面/zhanglei/整合/TOP.VHD" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "IO_DS\[2\] GND " "Warning: Pin \"IO_DS\[2\]\" stuck at GND" {  } { { "TOP.VHD" "" { Text "d:/我的文档/桌面/zhanglei/整合/TOP.VHD" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "IO_DS\[3\] GND " "Warning: Pin \"IO_DS\[3\]\" stuck at GND" {  } { { "TOP.VHD" "" { Text "d:/我的文档/桌面/zhanglei/整合/TOP.VHD" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "IO_DS\[4\] VCC " "Warning: Pin \"IO_DS\[4\]\" stuck at VCC" {  } { { "TOP.VHD" "" { Text "d:/我的文档/桌面/zhanglei/整合/TOP.VHD" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "IO_DS\[5\] GND " "Warning: Pin \"IO_DS\[5\]\" stuck at GND" {  } { { "TOP.VHD" "" { Text "d:/我的文档/桌面/zhanglei/整合/TOP.VHD" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "IO_DS\[6\] GND " "Warning: Pin \"IO_DS\[6\]\" stuck at GND" {  } { { "TOP.VHD" "" { Text "d:/我的文档/桌面/zhanglei/整合/TOP.VHD" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "171 " "Info: Implemented 171 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "145 " "Info: Implemented 145 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Nov 08 17:32:11 2008 " "Info: Processing ended: Sat Nov 08 17:32:11 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}