top.tan.summary

利用VHDL编写的电子琴发生器

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 15.400 ns
From           : INDEX1[3]
To             : Speaker1:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5]
From Clock     : --
To Clock       : CLK12MHZ1
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 17.300 ns
From           : Speaker1:u2|SpkS
To             : SPKOUT1
From Clock     : CLK12MHZ1
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 20.300 ns
From           : INDEX1[1]
To             : CODE1[2]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.100 ns
From           : INDEX1[4]
To             : Speaker1:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[7]
From Clock     : --
To Clock       : CLK12MHZ1
Failed Paths   : 0

Type           : Clock Setup: 'CLK12MHZ1'
Slack          : N/A
Required Time  : None
Actual Time    : 88.50 MHz ( period = 11.300 ns )
From           : Speaker1:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5]
To             : Speaker1:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[6]
From Clock     : CLK12MHZ1
To Clock       : CLK12MHZ1
Failed Paths   : 0

Type           : Clock Setup: 'HORL1'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 200.00 MHz ( period = 5.000 ns )
From           : Tone:u1|KLK[1]
To             : Tone:u1|KLK[1]
From Clock     : HORL1
To Clock       : HORL1
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------