mux21a.tan.rpt

利用VHDL编写的电子琴发生器

; Worst-case tco               ; N/A                                      ; None          ; 29.500 ns                                      ; Songer:u2|ToneTaba:u2|CODE[2]                                                     ; CODE2[2]                                                                                     ; CLK12MHZ2  ; --        ; 0            ;
; Worst-case tpd               ; N/A                                      ; None          ; 23.800 ns                                      ; INDEX3[5]                                                                         ; CODE2[2]                                                                                     ; --         ; --        ; 0            ;
; Worst-case th                ; N/A                                      ; None          ; -3.900 ns                                      ; INDEX3[4]                                                                         ; TOP:u1|Speaker1:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[7] ; --         ; CLK12MHZ2 ; 0            ;
; Clock Setup: 'CLK12MHZ2'     ; N/A                                      ; None          ; 69.44 MHz ( period = 14.400 ns )               ; Songer:u2|lpm_counter:count8Hz_rtl_5|alt_counter_f10ke:wysi_counter|q[4]          ; Songer:u2|CLK8HZ                                                                             ; CLK12MHZ2  ; CLK12MHZ2 ; 0            ;
; Clock Setup: 'HORL2'         ; N/A                                      ; None          ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; TOP:u1|Tone:u1|KLK[1]                                                             ; TOP:u1|Tone:u1|KLK[1]                                                                        ; HORL2      ; HORL2     ; 0            ;
; Clock Hold: 'CLK12MHZ2'      ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; Songer:u2|NoteTabs:u1|music:u1|lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra0 ; Songer:u2|ToneTaba:u2|HIGH                                                                   ; CLK12MHZ2  ; CLK12MHZ2 ; 416          ;
; Total number of failed paths ;                                          ;               ;                                                ;                                                                                   ;                                                                                              ;            ;           ; 416          ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+-----------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+------------+-----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1K30QC208-3      ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; HORL2           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; CLK12MHZ2       ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'HORL2'                                                                                                                                                                                               ;