organ.vhd

利用VHDL编写的电子琴发生器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ORGAN IS                                     -- 顶层设计
    PORT (   CLK12MHz,HOLD_SW1 : IN STD_LOGIC;
               ORGAN_INDEX       : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
               ORGAN_CODE        : OUT INTEGER RANGE 0 TO 15;
               TONE_HL        : OUT STD_LOGIC; 
               SW_DISP1        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
             ORGAN_OUT         : OUT STD_LOGIC );
 END;
ARCHITECTURE A OF ORGAN IS
       COMPONENT MUSIC_FREQ
         PORT ( Index : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
                MUSIC_CODE  : OUT INTEGER RANGE 0 TO 15;
                TONE_HL  : OUT STD_LOGIC; 
                HOLD_SW  : IN  STD_LOGIC; 
                SW_DISP  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                MUSIC_FREQ_OUT  : OUT INTEGER RANGE 0 TO 16#7FF#  ); --11位2进制数
    END COMPONENT;
    COMPONENT Speaker1
        PORT (  clk  :  IN STD_LOGIC;
                MUSIC_FREQ_IN :  IN INTEGER RANGE 0 TO 16#7FF#;             --11位2进制数
                SPEAKER : OUT STD_LOGIC  );
    END COMPONENT;
    SIGNAL MUSIC_FREQ_IN1 : INTEGER RANGE 0 TO 16#7FF#;
  BEGIN                    -- 安装U1, U2
u1 : MUSIC_FREQ    PORT MAP (Index=>ORGAN_INDEX, MUSIC_FREQ_OUT=>MUSIC_FREQ_IN1,MUSIC_CODE=>ORGAN_CODE,
                        TONE_HL=>TONE_HL,HOLD_SW=>HOLD_SW1,SW_DISP=>SW_DISP1);
u2 : Speaker1 PORT MAP (clk=>CLK12MHz,MUSIC_FREQ_IN=>MUSIC_FREQ_IN1, SPEAKER=>ORGAN_OUT );
END A;