📄 top.map.rpt
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; |lpm_counter:\DivideCLK:Count4[0]_rtl_1| ; 4 (0) ; 4 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (0) ; 4 (0) ; 0 (0) ; |TOP|Speaker1:u2|lpm_counter:\DivideCLK:Count4[0]_rtl_1 ;
; |alt_counter_f10ke:wysi_counter| ; 4 (4) ; 4 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 4 (4) ; 0 (0) ; |TOP|Speaker1:u2|lpm_counter:\DivideCLK:Count4[0]_rtl_1|alt_counter_f10ke:wysi_counter ;
; |lpm_counter:\GenSpkS:Count11[0]_rtl_0| ; 11 (0) ; 11 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 11 (0) ; 11 (0) ; 0 (0) ; |TOP|Speaker1:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0 ;
; |alt_counter_f10ke:wysi_counter| ; 11 (11) ; 11 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 11 (11) ; 11 (11) ; 0 (0) ; |TOP|Speaker1:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_f10ke:wysi_counter ;
; |Tone:u1| ; 123 (123) ; 2 ; 0 ; 0 ; 121 (121) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 (0) ; |TOP|Tone:u1 ;
+------------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 19 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 11 ;
; Number of registers using Asynchronous Clear ; 4 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+----------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: Speaker1:u2|lpm_counter:\GenSpkS:Count11[0]_rtl_0 ;
+------------------------+-------------------+-------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------------+-------------------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 11 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ;
; DEVICE_FAMILY ; ACEX1K ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+-------------------+-------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-----------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: Speaker1:u2|lpm_counter:\DivideCLK:Count4[0]_rtl_1 ;
+------------------------+-------------------+--------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------------+--------------------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 4 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ;
; DEVICE_FAMILY ; ACEX1K ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+-------------------+--------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in d:/我的文档/桌面/zhanglei/整合/top.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Sat Nov 08 17:32:05 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top
Info: Found 2 design units, including 1 entities, in source file music.vhd
Info: Found design unit 1: music-SYN
Info: Found entity 1: music
Info: Found 2 design units, including 1 entities, in source file music_freq.vhd
Info: Found design unit 1: MUSIC_FREQ-a
Info: Found entity 1: MUSIC_FREQ
Info: Found 2 design units, including 1 entities, in source file mux21a.vhd
Info: Found design unit 1: mux21a-ONE
Info: Found entity 1: mux21a
Info: Found 2 design units, including 1 entities, in source file NoteTabs.vhd
Info: Found design unit 1: NoteTabs-one
Info: Found entity 1: NoteTabs
Info: Found 2 design units, including 1 entities, in source file organ.vhd
Info: Found design unit 1: ORGAN-A
Info: Found entity 1: ORGAN
Info: Found 2 design units, including 1 entities, in source file Songer.vhd
Info: Found design unit 1: Songer-one
Info: Found entity 1: Songer
Info: Found 2 design units, including 1 entities, in source file speaker1.vhd
Info: Found design unit 1: Speaker1-one
Info: Found entity 1: Speaker1
Info: Found 2 design units, including 1 entities, in source file Speakera.vhd
Info: Found design unit 1: Speakera-one
Info: Found entity 1: Speakera
Info: Found 2 design units, including 1 entities, in source file TONE.VHD
Info: Found design unit 1: Tone-one
Info: Found entity 1: Tone
Info: Found 2 design units, including 1 entities, in source file ToneTaba.vhd
Info: Found design unit 1: ToneTaba-one
Info: Found entity 1: ToneTaba
Info: Found 2 design units, including 1 entities, in source file TOP.VHD
Info: Found design unit 1: TOP-one
Info: Found entity 1: TOP
Info: Elaborating entity "top" for the top level hierarchy
Info: Elaborating entity "Tone" for hierarchy "Tone:u1"
Warning (10492): VHDL Process Statement warning at TONE.VHD(19): signal "KLK" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at TONE.VHD(23): signal "KLK" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at TONE.VHD(35): signal "KLK" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at TONE.VHD(47): signal "KLK" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "Speaker1" for hierarchy "Speaker1:u2"
Info: Inferred 2 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=11) from the following logic: "Speaker1:u2|\GenSpkS:Count11[0]~0"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "Speaker1:u2|\DivideCLK:Count4[0]~0"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf
Info: Found entity 1: alt_counter_f10ke
Info: Duplicate registers merged to single register
Info: Duplicate register "Speaker1:u2|\DelaySpkS:Count2" merged to single register "Speaker1:u2|SpkS"
Warning: Output pins are stuck at VCC or GND
Warning: Pin "NUME1[2]" stuck at GND
Warning: Pin "NUME1[3]" stuck at GND
Warning: Pin "IO_DS[1]" stuck at VCC
Warning: Pin "IO_DS[2]" stuck at GND
Warning: Pin "IO_DS[3]" stuck at GND
Warning: Pin "IO_DS[4]" stuck at VCC
Warning: Pin "IO_DS[5]" stuck at GND
Warning: Pin "IO_DS[6]" stuck at GND
Info: Implemented 171 device resources after synthesis - the final resource count might be different
Info: Implemented 10 input pins
Info: Implemented 16 output pins
Info: Implemented 145 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 13 warnings
Info: Processing ended: Sat Nov 08 17:32:11 2008
Info: Elapsed time: 00:00:07
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