receiver.v.bak

简单的uart状态机的编写

module receiver(in_clk,
              in_resetn,
              in_bit,
              out_Data,
              out_DataEnable,
              out_ParityError,
              out_FrameError
              );
input in_clk;
input in_resetn;
input in_bit;
output [7:0] out_Data;

output out_DataEnable;
output out_ParityError;
output out_FrameError;
reg [63:0] DetectSequence;
reg [3:0] ClkCounter;
reg [4:0] st, next_st;
reg [7:0] out_Data;
reg [7:0] store_data;
reg      Parity;
reg      Frame;
reg      out_DataEnable;
reg      out_ParityError;
reg      out_FrameError;

parameter IDLE=0, D1=1,D2=2,D3=3,D4=4,D5=5,D6=6,D7=7,D8=8,PARITY=9,STOP1=10,STOP2=11,STOP3=12,STOP4=13;

//detect
always @(posedge in_clk or negedge in_resetn)
   if(!in_resetn)
      DetectSequence <= 0;
   else
      DetectSequence <= { DetectSequence [62:0],in_bit};
assign DetectNewFrame = (DetectSequence == 64'hFFFFFFFF00000000);

always @(posedge in_clk or negedge in_resetn)
   if(!in_resetn)
      ClkCounter <= 0;
   else if (DetectNewFrame)
      ClkCounter <= 0;
   else
      ClkCounter <= ClkCounter + 1'b1;

always @(posedge in_clk or negedge in_resetn)
   if(!in_resetn)
       st <= IDLE;
   else 
       st <= next_st;

always @(ClkCounter or st or DetectNewFrame)
   if(ClkCounter != 0)
       next_st <= st;
   else 
      case(st)
        IDLE: if (DetectNewFrame) next_st = D1;
        D1: next_st = D2;
        D2: next_st = D3;
        D3: next_st =D4;
        D4:next_st = D5;
        D5: next_st =D6;
        D6: next_st = D7;
        D7: next_st =D8;
        D8: next_st = PARITY;
        PARITY: next_st = STOP1;
        STOP1:next_st = STOP2;
        STOP2: next_st = STOP3;
        STOP3: next_st = STOP4;
        STOP4: next_st = IDLE;
        default: next_st = IDLE;
        endcase 

always @(posedge in_clk or negedge in_resetn)
if(!in_resetn)
   begin
      out_Data=0;
      Parity=0;
      out_FrameError=0;
   end
else if(ClkCounter ==8)
    case(st)  
      D1: store_data[7]=in_bit;
      D2: store_data[6]=in_bit;
      D3: store_data[5]=in_bit;
      D4: store_data[4]=in_bit;
      D5: store_data[3]=in_bit;
      D6: store_data[2]=in_bit;
      D7: store_data[1]= in_bit;
      D8:
         begin 
         store_data[0]=in_bit;
         out_Data[7:0] = store_data[7:0];
        end 
      PARITY: Parity=in_bit;
      STOP1: if(in_bit) out_FrameError =1;
               
      STOP2: if(in_bit) out_FrameError =1;
               
      STOP3: if(!in_bit) out_FrameError =1;
              
      STOP4: if(!in_bit) out_FrameError =1;
              
    endcase

always @(st or in_bit or Parity or out_Data)
   if((st == STOP4) & (in_bit))
     begin
        out_DataEnable = 1;
        out_ParityError = (Parity != ^out_Data);
     end
   else
     begin
        out_DataEnable = 0;
        out_ParityError = 0;
     end
endmodule