transmitter.v.bak

简单的uart状态机的编写

module transmitter(in_clk,
                in_resetn,
                in_Data,
                in_DataEnable,
                out_NextData,
                out_Bit
                );
input in_clk;
input in_resetn;
input in_DataEnable;
input [7:0] in_Data;
output out_NextData;
output out_Bit;

parameter IDLE=16,STOP1=10,STOP2=11,STOP3=12,STOP4=13,START1=14,START2=15,START=1,D1=1,D2=2,D3=3,D4=4,D5=5,D6=6,D7=7,D8=8,PARITY=9;
reg [3:0] st, next_st;
reg [3:0] ClkCounter;
reg [8:0] StoredData;
reg out_NextData;
reg out_Bit;
reg oBit;

always @(posedge in_clk or negedge in_resetn)
if(!in_resetn)
    st <= IDLE;
else
    st <= next_st;

always @(posedge in_clk or negedge in_resetn)
   if(!in_resetn)
      ClkCounter <= 0;
   else
      ClkCounter <= ClkCounter + 1;

always @(ClkCounter or st or in_DataEnable)
   if(ClkCounter != 0)
       next_st =st;
   else
 case(st)
    IDLE: if(in_DataEnable) next_st = STOP3;
    STOP3: next_st = STOP4;
    STOP4: next_st =START1;
    START1: next_st = START2;
    START2: next_st = D1;
    D1: next_st = D2;
    D2: next_st = D3;
    D3: next_st =D4;
    D4:next_st = D5;
    D5: next_st =D6;
    D6: next_st = D7;
    D7: next_st =D8;
    D8: next_st = PARITY;
    PARITY: next_st = STOP1;
    STOP1:next_st = STOP2;
    STOP2: next_st = STOP3;
    STOP3: next_st = STOP4;
    default: next_st = STOP3;
      endcase

always @(posedge in_clk or negedge in_resetn)
     if(!in_resetn)
        StoredData <= 0;
     else if(in_DataEnable)
        StoredData <= {in_Data,^in_Data};

always @(st or StoredData)
   case(st)
		  IDLE: oBit=1;
        STOP1,STOP2: oBit = 0;
        STOP3,STOP4: oBit = 1;
        START1,START2:oBit = 0;
        D1:oBit = StoredData[8];
        D2:oBit = StoredData[7];
        D3:oBit = StoredData[6];
        D4:oBit = StoredData[5];
        D5:oBit = StoredData[4];
        D6:oBit = StoredData[3];
        D7:oBit = StoredData[2];
        D8:oBit = StoredData[1];
        PARITY:oBit = StoredData[0];
        default: oBit = 1;
    endcase
always @(posedge in_clk or negedge in_resetn)
if(!in_resetn)
    out_Bit <= 1;
else 
    out_Bit <= oBit;
  
always @(st)
   if(st==STOP4)
      out_NextData =1;
   else
      out_NextData =0;

endmodule