_primary.vhd

来自「简单的uart状态机的编写」· VHDL 代码 · 共 35 行

library verilog;
use verilog.vl_types.all;
entity receiver2 is
    generic(
        IDLE            : integer := 0;
        D1              : integer := 1;
        D2              : integer := 2;
        D3              : integer := 3;
        D4              : integer := 4;
        D5              : integer := 5;
        D6              : integer := 6;
        D7              : integer := 7;
        D8              : integer := 8;
        PARITY          : integer := 9;
        STOP1           : integer := 10;
        STOP2           : integer := 11;
        STOP3           : integer := 12;
        STOP4           : integer := 13;
        DELAY1          : integer := 14;
        DELAY2          : integer := 15;
        DELAY3          : integer := 16;
        DELAY4          : integer := 17
    );
    port(
        in_clk          : in     vl_logic;
        in_resetn       : in     vl_logic;
        in_bit          : in     vl_logic;
        out_Data        : out    vl_logic_vector(7 downto 0);
        out_DataEnable  : out    vl_logic;
        out_ParityError : out    vl_logic;
        out_FrameError  : out    vl_logic;
        out_DelayError  : out    vl_logic
    );
end receiver2;