unicntr.vhd

通用寄存器

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY unicntr IS
  GENERIC(n: positive :=8);
  PORT( clock: IN std_logic;
        mode: IN std_logic_vector(2 DOWNTO 0);
        serinl: IN std_logic;
        serinr: IN std_logic;
        datain: IN std_logic_vector((n-1) DOWNTO 0);
        
        termcnt: OUT std_logic;
        dataout: OUT std_logic_vector((n-1) DOWNTO 0));
END unicntr;

ARCHITECTURE v1 OF unicntr IS
  SIGNAL int_reg: std_logic_vector((n-1) DOWNTO 0);

BEGIN  
  PROCESS(clock)
  BEGIN
  
    IF (RISING_EDGE(clock)) THEN
      CASE mode IS
        WHEN "000" => int_reg <= (OTHERS => '0'); --rst
        WHEN "001" => int_reg <= datain; --parallel load
        WHEN "010" => int_reg <= int_reg+1; --count up
        WHEN "011" => int_reg <= int_reg-1; --count down
        WHEN "100" => int_reg <= int_reg((n-2) DOWNTO 0) & serinl; --shift left
        WHEN "101" => int_reg <= serinr & int_reg((n-1) DOWNTO 1); --shift right
        WHEN OTHERS => NULL; --do nothing
      END CASE;
    END IF;
    
  END PROCESS;
  
  PROCESS(int_reg)
  BEGIN
    termcnt<='1';
    FOR i IN int_reg'RANGE LOOP
      IF int_reg(i)='1' THEN
        termcnt<='0';
        EXIT;
      END IF;
    END LOOP;
  END PROCESS;
    
  dataout<=int_reg;

END v1;