couter1.rpt
来自「用VHDL语言实现通用计算器设计」· RPT 代码 · 共 525 行 · 第 1/2 页
RPT
525 行
- 3 - B 08 AND2 0 3 0 3 |couter:1|lpm_counter:lpm_counter_component|f8count:p8c0|:289
- 4 - B 08 AND2 0 3 0 3 |couter:1|lpm_counter:lpm_counter_component|f8count:p8c0|:293
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\work\couter1.rpt
couter1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 3/ 96( 3%) 5/ 48( 10%) 0/ 48( 0%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\work\couter1.rpt
couter1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 a
Device-Specific Information: c:\work\couter1.rpt
couter1
** EQUATIONS **
a : INPUT;
-- Node name is 'b0'
-- Equation name is 'b0', type is output
b0 = _LC1_B2;
-- Node name is 'b1'
-- Equation name is 'b1', type is output
b1 = _LC4_B2;
-- Node name is 'b2'
-- Equation name is 'b2', type is output
b2 = _LC6_B8;
-- Node name is 'b3'
-- Equation name is 'b3', type is output
b3 = _LC5_B8;
-- Node name is 'b4'
-- Equation name is 'b4', type is output
b4 = _LC1_B8;
-- Node name is 'b5'
-- Equation name is 'b5', type is output
b5 = _LC2_B8;
-- Node name is 'b6'
-- Equation name is 'b6', type is output
b6 = _LC8_B8;
-- Node name is 'b7'
-- Equation name is 'b7', type is output
b7 = _LC7_B8;
-- Node name is '|couter:1|lpm_counter:lpm_counter_component|f8count:p8c0|:8' = '|couter:1|lpm_counter:lpm_counter_component|f8count:p8c0|QA'
-- Equation name is '_LC1_B2', type is buried
_LC1_B2 = DFFE(!_LC1_B2, GLOBAL( a), VCC, VCC, VCC);
-- Node name is '|couter:1|lpm_counter:lpm_counter_component|f8count:p8c0|:7' = '|couter:1|lpm_counter:lpm_counter_component|f8count:p8c0|QB'
-- Equation name is '_LC4_B2', type is buried
_LC4_B2 = DFFE( _EQ001, GLOBAL( a), VCC, VCC, VCC);
_EQ001 = !_LC1_B2 & _LC4_B2
# _LC1_B2 & !_LC4_B2;
-- Node name is '|couter:1|lpm_counter:lpm_counter_component|f8count:p8c0|:6' = '|couter:1|lpm_counter:lpm_counter_component|f8count:p8c0|QC'
-- Equation name is '_LC6_B8', type is buried
_LC6_B8 = DFFE( _EQ002, GLOBAL( a), VCC, VCC, VCC);
_EQ002 = !_LC4_B2 & _LC6_B8
# !_LC1_B2 & _LC6_B8
# _LC1_B2 & _LC4_B2 & !_LC6_B8;
-- Node name is '|couter:1|lpm_counter:lpm_counter_component|f8count:p8c0|:5' = '|couter:1|lpm_counter:lpm_counter_component|f8count:p8c0|QD'
-- Equation name is '_LC5_B8', type is buried
_LC5_B8 = DFFE( _EQ003, GLOBAL( a), VCC, VCC, VCC);
_EQ003 = !_LC3_B8 & _LC5_B8
# _LC3_B8 & !_LC5_B8;
-- Node name is '|couter:1|lpm_counter:lpm_counter_component|f8count:p8c0|:4' = '|couter:1|lpm_counter:lpm_counter_component|f8count:p8c0|QE'
-- Equation name is '_LC1_B8', type is buried
_LC1_B8 = DFFE( _EQ004, GLOBAL( a), VCC, VCC, VCC);
_EQ004 = _LC1_B8 & !_LC5_B8
# _LC1_B8 & !_LC3_B8
# !_LC1_B8 & _LC3_B8 & _LC5_B8;
-- Node name is '|couter:1|lpm_counter:lpm_counter_component|f8count:p8c0|:3' = '|couter:1|lpm_counter:lpm_counter_component|f8count:p8c0|QF'
-- Equation name is '_LC2_B8', type is buried
_LC2_B8 = DFFE( _EQ005, GLOBAL( a), VCC, VCC, VCC);
_EQ005 = _LC2_B8 & !_LC4_B8
# !_LC2_B8 & _LC4_B8;
-- Node name is '|couter:1|lpm_counter:lpm_counter_component|f8count:p8c0|:2' = '|couter:1|lpm_counter:lpm_counter_component|f8count:p8c0|QG'
-- Equation name is '_LC8_B8', type is buried
_LC8_B8 = DFFE( _EQ006, GLOBAL( a), VCC, VCC, VCC);
_EQ006 = !_LC2_B8 & _LC8_B8
# !_LC4_B8 & _LC8_B8
# _LC2_B8 & _LC4_B8 & !_LC8_B8;
-- Node name is '|couter:1|lpm_counter:lpm_counter_component|f8count:p8c0|:1' = '|couter:1|lpm_counter:lpm_counter_component|f8count:p8c0|QH'
-- Equation name is '_LC7_B8', type is buried
_LC7_B8 = DFFE( _EQ007, GLOBAL( a), VCC, VCC, VCC);
_EQ007 = !_LC2_B8 & _LC7_B8
# !_LC4_B8 & _LC7_B8
# _LC7_B8 & !_LC8_B8
# _LC2_B8 & _LC4_B8 & !_LC7_B8 & _LC8_B8;
-- Node name is '|couter:1|lpm_counter:lpm_counter_component|f8count:p8c0|:289'
-- Equation name is '_LC3_B8', type is buried
_LC3_B8 = LCELL( _EQ008);
_EQ008 = _LC1_B2 & _LC4_B2 & _LC6_B8;
-- Node name is '|couter:1|lpm_counter:lpm_counter_component|f8count:p8c0|:293'
-- Equation name is '_LC4_B8', type is buried
_LC4_B8 = LCELL( _EQ009);
_EQ009 = _LC1_B8 & _LC3_B8 & _LC5_B8;
Project Information c:\work\couter1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 9,989K
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