div84.vhd

来自「用VHDL语言实现通用计算器设计」· VHDL 代码 · 共 17 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity div84 is
port(
adata : in std_logic_vector( 7 downto 0);
bdata : in std_logic_vector(7 downto 0);
result: out std_logic_vector( 7 downto 0)
);
end div84;

architecture abc of div84 is
begin
result<=mod(adata,bdata);
end abc;