mux21.rpt
来自「用VHDL语言实现通用计算器设计」· RPT 代码 · 共 554 行 · 第 1/2 页
RPT
554 行
- 2 - B 07 OR2 s 3 0 0 1 |mux12:1|lpm_mux:lpm_mux_component|muxlut:120|~46~1
- 3 - B 07 OR2 s 3 0 0 1 |mux12:1|lpm_mux:lpm_mux_component|muxlut:120|~51~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\work\mux21.rpt
mux21
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 6/ 96( 6%) 6/ 48( 12%) 0/ 48( 0%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
B: 4/ 96( 4%) 1/ 48( 2%) 0/ 48( 0%) 4/16( 25%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\work\mux21.rpt
mux21
** EQUATIONS **
datin00 : INPUT;
datin01 : INPUT;
datin02 : INPUT;
datin03 : INPUT;
datin10 : INPUT;
datin11 : INPUT;
datin12 : INPUT;
datin13 : INPUT;
datin20 : INPUT;
datin21 : INPUT;
datin22 : INPUT;
datin23 : INPUT;
datin30 : INPUT;
datin31 : INPUT;
datin32 : INPUT;
datin33 : INPUT;
sel10 : INPUT;
sel11 : INPUT;
-- Node name is 're10'
-- Equation name is 're10', type is output
re10 = _LC3_A7;
-- Node name is 're11'
-- Equation name is 're11', type is output
re11 = _LC5_A7;
-- Node name is 're12'
-- Equation name is 're12', type is output
re12 = _LC7_A7;
-- Node name is 're13'
-- Equation name is 're13', type is output
re13 = _LC1_B7;
-- Node name is '|mux12:1|lpm_mux:lpm_mux_component|muxlut:66|result_node' from file "muxlut.tdf" line 173, column 80
-- Equation name is '_LC3_A7', type is buried
_LC3_A7 = LCELL( _EQ001);
_EQ001 = _LC4_B7 & !sel11
# _LC1_A7 & _LC4_B7
# _LC1_A7 & sel11;
-- Node name is '|mux12:1|lpm_mux:lpm_mux_component|muxlut:66|~46~1' from file "muxlut.tdf" line 173, column 56
-- Equation name is '_LC1_A7', type is buried
-- synthesized logic cell
_LC1_A7 = LCELL( _EQ002);
_EQ002 = datin30 & sel10
# datin20 & !sel10;
-- Node name is '|mux12:1|lpm_mux:lpm_mux_component|muxlut:66|~51~1' from file "muxlut.tdf" line 174, column 50
-- Equation name is '_LC4_B7', type is buried
-- synthesized logic cell
_LC4_B7 = LCELL( _EQ003);
_EQ003 = datin10 & sel10
# datin00 & !sel10;
-- Node name is '|mux12:1|lpm_mux:lpm_mux_component|muxlut:84|result_node' from file "muxlut.tdf" line 173, column 80
-- Equation name is '_LC5_A7', type is buried
_LC5_A7 = LCELL( _EQ004);
_EQ004 = _LC2_A7 & _LC4_A7
# _LC2_A7 & sel11
# _LC4_A7 & !sel11;
-- Node name is '|mux12:1|lpm_mux:lpm_mux_component|muxlut:84|~46~1' from file "muxlut.tdf" line 173, column 56
-- Equation name is '_LC2_A7', type is buried
-- synthesized logic cell
_LC2_A7 = LCELL( _EQ005);
_EQ005 = datin31 & sel10
# datin21 & !sel10;
-- Node name is '|mux12:1|lpm_mux:lpm_mux_component|muxlut:84|~51~1' from file "muxlut.tdf" line 174, column 50
-- Equation name is '_LC4_A7', type is buried
-- synthesized logic cell
_LC4_A7 = LCELL( _EQ006);
_EQ006 = datin11 & sel10
# datin01 & !sel10;
-- Node name is '|mux12:1|lpm_mux:lpm_mux_component|muxlut:102|result_node' from file "muxlut.tdf" line 173, column 80
-- Equation name is '_LC7_A7', type is buried
_LC7_A7 = LCELL( _EQ007);
_EQ007 = _LC6_A7 & _LC8_A7
# _LC6_A7 & sel11
# _LC8_A7 & !sel11;
-- Node name is '|mux12:1|lpm_mux:lpm_mux_component|muxlut:102|~46~1' from file "muxlut.tdf" line 173, column 56
-- Equation name is '_LC6_A7', type is buried
-- synthesized logic cell
_LC6_A7 = LCELL( _EQ008);
_EQ008 = datin32 & sel10
# datin22 & !sel10;
-- Node name is '|mux12:1|lpm_mux:lpm_mux_component|muxlut:102|~51~1' from file "muxlut.tdf" line 174, column 50
-- Equation name is '_LC8_A7', type is buried
-- synthesized logic cell
_LC8_A7 = LCELL( _EQ009);
_EQ009 = datin12 & sel10
# datin02 & !sel10;
-- Node name is '|mux12:1|lpm_mux:lpm_mux_component|muxlut:120|result_node' from file "muxlut.tdf" line 173, column 80
-- Equation name is '_LC1_B7', type is buried
_LC1_B7 = LCELL( _EQ010);
_EQ010 = _LC2_B7 & _LC3_B7
# _LC2_B7 & sel11
# _LC3_B7 & !sel11;
-- Node name is '|mux12:1|lpm_mux:lpm_mux_component|muxlut:120|~46~1' from file "muxlut.tdf" line 173, column 56
-- Equation name is '_LC2_B7', type is buried
-- synthesized logic cell
_LC2_B7 = LCELL( _EQ011);
_EQ011 = datin33 & sel10
# datin23 & !sel10;
-- Node name is '|mux12:1|lpm_mux:lpm_mux_component|muxlut:120|~51~1' from file "muxlut.tdf" line 174, column 50
-- Equation name is '_LC3_B7', type is buried
-- synthesized logic cell
_LC3_B7 = LCELL( _EQ012);
_EQ012 = datin13 & sel10
# datin03 & !sel10;
Project Information c:\work\mux21.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 10,597K
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