ymq.rpt

交通灯控制系统VHDL源码

A:       2/ 96(  2%)     3/ 48(  6%)     2/ 48(  4%)    0/16(  0%)      6/16( 37%)     0/16(  0%)
B:       0/ 96(  0%)     1/ 48(  2%)     0/ 48(  0%)    0/16(  0%)      1/16(  6%)     0/16(  0%)
C:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                         d:\max2work\jtdkz\ymq.rpt
ymq

** EQUATIONS **

AIN40    : INPUT;
AIN41    : INPUT;
AIN42    : INPUT;
AIN43    : INPUT;

-- Node name is 'DOUT70' 
-- Equation name is 'DOUT70', type is output 
DOUT70   =  _LC8_A12;

-- Node name is 'DOUT71' 
-- Equation name is 'DOUT71', type is output 
DOUT71   =  _LC1_A19;

-- Node name is 'DOUT72' 
-- Equation name is 'DOUT72', type is output 
DOUT72   =  _LC2_A12;

-- Node name is 'DOUT73' 
-- Equation name is 'DOUT73', type is output 
DOUT73   =  _LC1_A12;

-- Node name is 'DOUT74' 
-- Equation name is 'DOUT74', type is output 
DOUT74   =  _LC5_A19;

-- Node name is 'DOUT75' 
-- Equation name is 'DOUT75', type is output 
DOUT75   =  _LC8_A19;

-- Node name is 'DOUT76' 
-- Equation name is 'DOUT76', type is output 
DOUT76   =  _LC4_B8;

-- Node name is ':320' 
-- Equation name is '_LC2_A19', type is buried 
_LC2_A19 = LCELL( _EQ001);
  _EQ001 = !AIN40 & !AIN41 &  AIN42 & !AIN43;

-- Node name is ':344' 
-- Equation name is '_LC6_A12', type is buried 
!_LC6_A12 = _LC6_A12~NOT;
_LC6_A12~NOT = LCELL( _EQ002);
  _EQ002 = !AIN41
         #  AIN43
         #  AIN40
         #  AIN42;

-- Node name is ':356' 
-- Equation name is '_LC3_A12', type is buried 
_LC3_A12 = LCELL( _EQ003);
  _EQ003 =  AIN40 & !AIN41 & !AIN42 & !AIN43;

-- Node name is ':368' 
-- Equation name is '_LC6_A19', type is buried 
_LC6_A19 = LCELL( _EQ004);
  _EQ004 = !AIN40 & !AIN41 & !AIN42 & !AIN43;

-- Node name is '~373~1' 
-- Equation name is '~373~1', location is LC4_A12, type is buried.
-- synthesized logic cell 
!_LC4_A12 = _LC4_A12~NOT;
_LC4_A12~NOT = LCELL( _EQ005);
  _EQ005 =  _LC3_A12
         #  _LC6_A19;

-- Node name is ':373' 
-- Equation name is '_LC4_B8', type is buried 
_LC4_B8  = LCELL( _EQ006);
  _EQ006 = !AIN40 &  AIN42 & !AIN43
         # !AIN41 &  AIN42 & !AIN43
         # !AIN40 &  AIN41 & !AIN43
         #  AIN41 & !AIN42 & !AIN43
         # !AIN41 & !AIN42 &  AIN43;

-- Node name is ':404' 
-- Equation name is '_LC8_A19', type is buried 
_LC8_A19 = LCELL( _EQ007);
  _EQ007 =  _LC3_A19 &  _LC7_A19
         #  _LC2_A19 &  _LC3_A19
         #  _LC6_A19;

-- Node name is '~406~1' 
-- Equation name is '~406~1', location is LC3_A19, type is buried.
-- synthesized logic cell 
!_LC3_A19 = _LC3_A19~NOT;
_LC3_A19~NOT = LCELL( _EQ008);
  _EQ008 =  AIN41 & !AIN42 & !AIN43
         #  AIN40 & !AIN42 & !AIN43;

-- Node name is '~433~1' 
-- Equation name is '~433~1', location is LC5_A12, type is buried.
-- synthesized logic cell 
!_LC5_A12 = _LC5_A12~NOT;
_LC5_A12~NOT = LCELL( _EQ009);
  _EQ009 = !AIN40 & !AIN41 &  AIN42 & !AIN43
         #  AIN40 &  AIN41 & !AIN42 & !AIN43;

-- Node name is ':437' 
-- Equation name is '_LC5_A19', type is buried 
_LC5_A19 = LCELL( _EQ010);
  _EQ010 = !AIN40 & !AIN42 & !AIN43
         # !AIN40 & !AIN41 & !AIN42
         # !AIN40 &  AIN41 & !AIN43;

-- Node name is ':455' 
-- Equation name is '_LC7_A19', type is buried 
_LC7_A19 = LCELL( _EQ011);
  _EQ011 = !AIN41 & !AIN42 &  AIN43
         #  AIN40 & !AIN41 &  AIN42 & !AIN43
         # !AIN40 &  AIN41 &  AIN42 & !AIN43;

-- Node name is ':470' 
-- Equation name is '_LC1_A12', type is buried 
_LC1_A12 = LCELL( _EQ012);
  _EQ012 = !AIN40 & !AIN42 & !AIN43
         #  AIN41 & !AIN42 & !AIN43
         # !AIN41 & !AIN42 &  AIN43
         # !AIN40 & !AIN41 & !AIN42
         # !AIN40 &  AIN41 & !AIN43
         #  AIN40 & !AIN41 &  AIN42 & !AIN43;

-- Node name is ':503' 
-- Equation name is '_LC2_A12', type is buried 
_LC2_A12 = LCELL( _EQ013);
  _EQ013 = !_LC4_A12
         # !_LC5_A12 & !_LC6_A12
         # !_LC6_A12 &  _LC7_A12;

-- Node name is ':526' 
-- Equation name is '_LC4_A19', type is buried 
_LC4_A19 = LCELL( _EQ014);
  _EQ014 = !AIN41 & !AIN42 &  AIN43
         #  AIN40 &  AIN41 &  AIN42 & !AIN43;

-- Node name is ':536' 
-- Equation name is '_LC1_A19', type is buried 
_LC1_A19 = LCELL( _EQ015);
  _EQ015 =  _LC6_A19
         #  _LC2_A19
         # !_LC3_A19
         #  _LC4_A19;

-- Node name is ':554' 
-- Equation name is '_LC7_A12', type is buried 
_LC7_A12 = LCELL( _EQ016);
  _EQ016 =  AIN40 &  AIN42 & !AIN43
         # !AIN41 & !AIN42 &  AIN43
         #  AIN41 &  AIN42 & !AIN43;

-- Node name is ':569' 
-- Equation name is '_LC8_A12', type is buried 
_LC8_A12 = LCELL( _EQ017);
  _EQ017 = !AIN40 & !AIN42 & !AIN43
         #  AIN40 &  AIN42 & !AIN43
         # !AIN41 & !AIN42 &  AIN43
         # !AIN40 & !AIN41 & !AIN42
         #  AIN41 & !AIN43;



Project Information                                  d:\max2work\jtdkz\ymq.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10KA' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 14,159K