📄 xskz.rpt
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Project Information d:\max2work\jtdkz\xskz.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 12/08/2007 14:36:14
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
XSKZ
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
xskz EPF10K10ATC100-1 44 16 0 0 0 % 56 9 %
User Pins: 44 16 0
Device-Specific Information: d:\max2work\jtdkz\xskz.rpt
xskz
***** Logic for device 'xskz' compiled without errors.
Device: EPF10K10ATC100-1
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
Device-Specific Information: d:\max2work\jtdkz\xskz.rpt
xskz
** ERROR SUMMARY **
Info: Chip 'xskz' in device 'EPF10K10ATC100-1' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
R R R R
A A E E E A A A A A E
I I A S D S A V S A I I D I I D I S ^
N N I E O E I E C E I N N V O N N O N E D
# 2 4 N R U R E N N C R N 4 2 C U 2 4 U 4 R A
T 5 5 0 V G T V G N 0 0 I V 0 5 5 C T 5 5 T 5 V T
C M B 5 E N M E N 2 5 5 N E 5 B M I B M M B B E A
K 5 5 5 D D 5 D D 5 6 B T D 1 1 3 O 3 1 6 6 2 D 0
----------------------------------------------------_
/ 100 98 96 94 92 90 88 86 84 82 80 78 76 |_
/ 99 97 95 93 91 89 87 85 83 81 79 77 |
^CONF_DONE | 1 75 | ^DCLK
^nCEO | 2 74 | ^nCE
#TDO | 3 73 | #TDI
VCCIO | 4 72 | GND
AIN057 | 5 71 | AIN25B4
AIN25M7 | 6 70 | DOUTM7
DOUTB4 | 7 69 | AIN45M4
DOUTM4 | 8 68 | DOUTM6
DOUTB7 | 9 67 | VCCIO
DOUTB5 | 10 66 | VCCINT
GND | 11 65 | DOUTM2
GND | 12 64 | AIN25B2
AIN053 | 13 EPF10K10ATC100-1 63 | DOUTB2
AIN45B6 | 14 62 | AIN45M2
AIN45M3 | 15 61 | DOUTM3
AIN25B3 | 16 60 | GND
VCCIO | 17 59 | GND
VCCINT | 18 58 | AIN45M1
AIN25B1 | 19 57 | DOUTB1
AIN45M0 | 20 56 | DOUTM1
DOUTB0 | 21 55 | AIN25M0
AIN45B0 | 22 54 | ^MSEL0
AIN25B0 | 23 53 | ^MSEL1
#TMS | 24 52 | VCCINT
^nSTATUS | 25 51 | ^nCONFIG
| 27 29 31 33 35 37 39 41 43 45 47 49 _|
\ 26 28 30 32 34 36 38 40 42 44 46 48 50 |
\-----------------------------------------------------
A R G A D A V A A A A V E A E G A A A A G A A V R
I E N I O I C I I I I C N I N N I I I I N I I C E
N S D N U N C N N N N C 0 N 4 D N N N N D N N C S
2 E 4 T 0 I 2 4 4 2 I 5 0 5 4 2 0 4 2 2 I E
5 R 5 M 5 O 5 5 5 5 N M 5 5 5 5 5 5 5 O R
M V B 0 0 B M B B T 4 B B 2 M M M V
4 E 7 5 5 4 7 3 6 7 6 2 E
D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is not '5.0 V'-tolerant.
Device-Specific Information: d:\max2work\jtdkz\xskz.rpt
xskz
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A9 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
A19 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 12/22( 54%)
A21 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 14/22( 63%)
B1 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 13/22( 59%)
B3 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
C4 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
C20 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 10/22( 45%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 54/60 ( 90%)
Total logic cells used: 56/576 ( 9%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.42/4 ( 85%)
Total fan-in: 192/2304 ( 8%)
Total input pins required: 44
Total input I/O cell registers required: 0
Total output pins required: 16
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 56
Total flipflops required: 0
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 0/ 576 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 8 0 8 0 0 0 24/0
B: 8 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16/0
C: 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 16/0
Total: 8 0 8 8 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 8 8 8 0 0 0 56/0
Device-Specific Information: d:\max2work\jtdkz\xskz.rpt
xskz
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
23 - - C -- INPUT 0 0 0 1 AIN25B0
19 - - C -- INPUT 0 0 0 1 AIN25B1
64 - - B -- INPUT 0 0 0 1 AIN25B2
16 - - B -- INPUT 0 0 0 1 AIN25B3
71 - - A -- INPUT 0 0 0 1 AIN25B4
33 - - - 17 INPUT 0 0 0 1 AIN25B5
43 - - - 11 INPUT 0 0 0 1 AIN25B6
36 - - - 14 INPUT 0 0 0 1 AIN25B7
55 - - C -- INPUT 0 0 0 1 AIN25M0
81 - - - 03 INPUT 0 0 0 1 AIN25M1
48 - - - 06 INPUT 0 0 0 1 AIN25M2
84 - - - 05 INPUT 0 0 0 1 AIN25M3
26 - - - 23 INPUT 0 0 0 1 AIN25M4
99 - - - 24 INPUT 0 0 0 1 AIN25M5
47 - - - 07 INPUT 0 0 0 1 AIN25M6
6 - - A -- INPUT 0 0 0 1 AIN25M7
22 - - C -- INPUT 0 0 0 1 AIN45B0
85 - - - 08 INPUT 0 0 0 1 AIN45B1
78 - - - 01 INPUT 0 0 0 1 AIN45B2
42 - - - 12 INPUT 0 0 0 1 AIN45B3
35 - - - 15 INPUT 0 0 0 1 AIN45B4
98 - - - 24 INPUT 0 0 0 1 AIN45B5
14 - - B -- INPUT 0 0 0 1 AIN45B6
29 - - - 20 INPUT 0 0 0 1 AIN45B7
20 - - C -- INPUT 0 0 0 1 AIN45M0
58 - - C -- INPUT 0 0 0 1 AIN45M1
62 - - B -- INPUT 0 0 0 1 AIN45M2
15 - - B -- INPUT 0 0 0 1 AIN45M3
69 - - A -- INPUT 0 0 0 1 AIN45M4
34 - - - 16 INPUT 0 0 0 1 AIN45M5
80 - - - 03 INPUT 0 0 0 1 AIN45M6
45 - - - 09 INPUT 0 0 0 1 AIN45M7
31 - - - 18 INPUT 0 0 0 3 AIN050
86 - - - 09 INPUT 0 0 0 3 AIN051
44 - - - 10 INPUT 0 0 0 3 AIN052
13 - - B -- INPUT 0 0 0 3 AIN053
39 - - - -- INPUT 0 0 0 3 AIN054
97 - - - 23 INPUT 0 0 0 3 AIN055
90 - - - -- INPUT 0 0 0 3 AIN056
5 - - A -- INPUT 0 0 0 3 AIN057
89 - - - -- INPUT 0 0 0 16 EN05B
38 - - - -- INPUT 0 0 0 24 EN05M
91 - - - -- INPUT 0 0 0 16 EN25
40 - - - -- INPUT 0 0 0 16 EN45
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\max2work\jtdkz\xskz.rpt
xskz
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
21 - - C -- OUTPUT 0 1 0 0 DOUTB0
57 - - C -- OUTPUT 0 1 0 0 DOUTB1
63 - - B -- OUTPUT 0 1 0 0 DOUTB2
82 - - - 04 OUTPUT 0 1 0 0 DOUTB3
7 - - A -- OUTPUT 0 1 0 0 DOUTB4
10 - - A -- OUTPUT 0 1 0 0 DOUTB5
79 - - - 02 OUTPUT 0 1 0 0 DOUTB6
9 - - A -- OUTPUT 0 1 0 0 DOUTB7
30 - - - 19 OUTPUT 0 1 0 0 DOUTM0
56 - - C -- OUTPUT 0 1 0 0 DOUTM1
65 - - B -- OUTPUT 0 1 0 0 DOUTM2
61 - - B -- OUTPUT 0 1 0 0 DOUTM3
8 - - A -- OUTPUT 0 1 0 0 DOUTM4
94 - - - 19 OUTPUT 0 1 0 0 DOUTM5
68 - - A -- OUTPUT 0 1 0 0 DOUTM6
70 - - A -- OUTPUT 0 1 0 0 DOUTM7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\max2work\jtdkz\xskz.rpt
xskz
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - A 09 OR2 2 1 0 1 :530
- 1 - A 09 AND2 2 0 0 2 :543
- 8 - A 09 OR2 3 1 0 1 :544
- 3 - A 09 OR2 2 2 1 1 :548
- 4 - A 09 OR2 2 1 0 1 :554
- 2 - A 09 AND2 2 0 0 2 :561
- 5 - A 09 OR2 3 1 0 1 :562
- 7 - A 09 OR2 2 2 1 1 :563
- 6 - A 19 OR2 2 1 0 1 :569
- 2 - A 19 AND2 2 0 0 2 :576
- 8 - A 19 OR2 3 1 0 1 :577
- 1 - A 19 OR2 2 2 1 1 :578
- 6 - A 21 OR2 2 1 0 1 :584
- 2 - C 20 AND2 2 0 0 2 :591
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