jtdkz.vhd

交通灯控制系统VHDL源码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY JTDKZ IS
  PORT(CLK,SM,SB:IN STD_LOGIC;
       MR,MY0,MG0,BR,BY0,BG0:OUT STD_LOGIC);
END ENTITY JTDKZ;

ARCHITECTURE ART OF JTDKZ IS
  TYPE STATE_TYPE IS(A,B,C,D);
  SIGNAL STATE:STATE_TYPE;
  BEGIN
  CNT:PROCESS(CLK) IS
    VARIABLE S:INTEGER RANGE 0 TO 45;
    VARIABLE CLR,EN:BIT;
    BEGIN
    IF(CLK'EVENT AND CLK='1') THEN
      IF CLR='0' THEN S:=0;
        ELSIF EN='0' THEN S:=S;
          ELSE S:=S+1;
      END IF;
      CASE STATE IS
      WHEN A=>MR<='0';MY0<='0';MG0<='1';BR<='1';BY0<='0';BG0<='0';
      IF(SB AND SM)='1' THEN
        IF S=45 THEN STATE<=B;CLR:='0';EN:='0';
          ELSE STATE<=A;CLR:='1';EN:='1';
        END IF;
      ELSIF(SB AND(NOT SM))='1' THEN STATE<=B;CLR:='0';EN:='0';
        ELSE STATE<=A;CLR:='1';EN:='1';
      END IF;
      WHEN B=>MR<='0';MY0<='1';MG0<='0';BR<='1';BY0<='0';BG0<='0';
      IF S=5 THEN STATE<=C;CLR:='0';EN:='0';
        ELSE STATE<=B;CLR:='1';EN:='1';
      END IF;
      WHEN C=>MR<='1';MY0<='0';MG0<='0';BR<='0';BY0<='0';BG0<='1';
      IF(SB AND SM)='1' THEN
        IF S=25 THEN STATE<=D;CLR:='0';EN:='0';
          ELSE STATE<=C;CLR:='1';EN:='1';
        END IF;
      ELSIF SB='0' THEN STATE<=D;CLR:='0';EN:='0';
        ELSE STATE<=C;CLR:='1';EN:='1';
      END IF;
      WHEN D=>MR<='1';MY0<='0';MG0<='0';BR<='0';BY0<='1';BG0<='0';
        IF S=5 THEN STATE<=A;CLR:='0';EN:='0';
          ELSE STATE<=D;CLR:='1';EN:='1';
        END IF;
        END CASE;
      END IF;
    END PROCESS CNT;
END ARCHITECTURE ART;