jtkzq.vhd

交通灯控制系统VHDL源码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY JTKZQ IS
  PORT(CLK,SM,SB:IN STD_LOGIC;
       MR,MG,MY,BY,BR,BG:OUT STD_LOGIC;
       DOUT1,DOUT2,DOUT3,DOUT4:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END ENTITY JTKZQ;
 
ARCHITECTURE ART OF JTKZQ IS
  COMPONENT JTDKZ IS
    PORT(CLK,SM,SB:IN STD_LOGIC;
       MR,MY0,MG0,BR,BY0,BG0:OUT STD_LOGIC);
  END COMPONENT JTDKZ;
  COMPONENT CSKZ IS
    PORT(INA:IN STD_LOGIC;
       OUTA:OUT STD_LOGIC);
  END COMPONENT CSKZ;
  COMPONENT CNT45S IS
  PORT(SB,CLK,EN45:IN STD_LOGIC;
       DOUT45M,DOUT45B:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
  END COMPONENT CNT45S;
  COMPONENT CNT05S IS
  PORT(CLK,EN05M,EN05B:IN STD_LOGIC;
       DOUT5:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
  END COMPONENT CNT05S;
  COMPONENT XSKZ IS
  PORT(EN45,EN25,EN05M,EN05B:IN STD_LOGIC;
       AIN45M,AIN45B,AIN25M,AIN25B,AIN05:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
       DOUTM,DOUTB:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
  END COMPONENT XSKZ;
  COMPONENT YMQ IS
  PORT(AIN4:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
       DOUT7:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
  END COMPONENT YMQ;
  COMPONENT CNT25S IS
  PORT(SB,SM,CLK,EN25:IN STD_LOGIC;
       DOUT25M,DOUT25B:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
  END COMPONENT CNT25S;



  SIGNAL EN1,EN2,EN3,EN4:STD_LOGIC;
  SIGNAL S45M,S45B,S05,S25M,S25B:STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL YM1,YM2,YM3,YM4:STD_LOGIC_VECTOR(3 DOWNTO 0);
  BEGIN
  U1:JTDKZ PORT MAP(CLK=>CLK,SM=>SM,SB=>SB,MR=>MR,MY0=>EN2,MG0=>EN1,BR=>BR,BY0=>EN4,BG0=>EN3);
  U2:CSKZ PORT MAP(INA=>EN1,OUTA=>MG);
  U3:CSKZ PORT MAP(INA=>EN2,OUTA=>MY);
  U4:CSKZ PORT MAP(INA=>EN3,OUTA=>BG);
  U5:CSKZ PORT MAP(INA=>EN4,OUTA=>BG);
  U6:CNT45S PORT MAP(CLK=>CLK,SB=>SB,EN45=>EN1,DOUT45M=>S45M,DOUT45B=>S45B);
  U7:CNT05S PORT MAP(CLK=>CLK,EN05M=>EN2,DOUT5=>S05,EN05B=>EN4);
  U8:CNT25S PORT MAP(CLK=>CLK,SM=>SM,SB=>SB,EN25=>EN3,DOUT25M=>S25M,DOUT25B=>S25B);
  U9:XSKZ PORT MAP(EN45=>EN1,EN25=>EN3,EN05M=>EN2,EN05B=>EN4,
                   AIN45M=>S45M,AIN45B=>S45B,AIN25M=>S25M,AIN25B=>S25B,AIN05=>S05,
                   DOUTM(3 DOWNTO 0)=>YM1,DOUTM(7 DOWNTO 4)=>YM2,DOUTB(3 DOWNTO 0)=>YM3,DOUTB(7 DOWNTO 4)=>YM4);
  U10:YMQ PORT MAP(AIN4=>YM1,DOUT7=>DOUT1);
  U11:YMQ PORT MAP(AIN4=>YM2,DOUT7=>DOUT2);
  U13:YMQ PORT MAP(AIN4=>YM3,DOUT7=>DOUT3);
  U14:YMQ PORT MAP(AIN4=>YM4,DOUT7=>DOUT4);
END ARCHITECTURE ART;