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📄 jtdkz.rpt

📁 交通灯控制系统VHDL源码
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Device-Specific Information:                       d:\max2work\jtdkz\jtdkz.rpt
jtdkz

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       15         CLK


Device-Specific Information:                       d:\max2work\jtdkz\jtdkz.rpt
jtdkz

** EQUATIONS **

CLK      : INPUT;
SB       : INPUT;
SM       : INPUT;

-- Node name is 'BG0' 
-- Equation name is 'BG0', type is output 
BG0      =  _LC5_A4;

-- Node name is 'BR' 
-- Equation name is 'BR', type is output 
BR       =  _LC3_A4;

-- Node name is 'BY0' 
-- Equation name is 'BY0', type is output 
BY0      =  _LC6_A4;

-- Node name is ':25' = 'EN' 
-- Equation name is 'EN', location is LC1_A5, type is buried.
EN       = DFFE( _EQ001, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ001 =  _LC3_A5
         #  _LC5_A5 & !STATE0 & !STATE1;

-- Node name is 'MG0' 
-- Equation name is 'MG0', type is output 
MG0      =  _LC1_A4;

-- Node name is 'MR' 
-- Equation name is 'MR', type is output 
MR       =  _LC7_A4;

-- Node name is 'MY0' 
-- Equation name is 'MY0', type is output 
MY0      =  _LC2_A4;

-- Node name is ':17' = 'STATE0' 
-- Equation name is 'STATE0', location is LC4_A5, type is buried.
STATE0   = DFFE( _EQ002, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ002 =  _LC7_A5
         #  _LC8_A5 & !STATE0 & !STATE1;

-- Node name is ':16' = 'STATE1' 
-- Equation name is 'STATE1', location is LC4_A4, type is buried.
STATE1   = DFFE( _EQ003, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ003 =  _LC2_A11 &  STATE0 & !STATE1
         # !STATE0 &  STATE1
         # !_LC2_A11 &  STATE1;

-- Node name is ':23' = 'S0' 
-- Equation name is 'S0', location is LC5_A10, type is buried.
S0       = DFFE( _EQ004, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ004 =  EN & !S0;

-- Node name is ':22' = 'S1' 
-- Equation name is 'S1', location is LC3_A10, type is buried.
S1       = DFFE( _EQ005, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ005 =  EN &  S0 & !S1
         #  EN & !S0 &  S1;

-- Node name is ':21' = 'S2' 
-- Equation name is 'S2', location is LC1_A2, type is buried.
S2       = DFFE( _EQ006, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ006 =  EN &  _LC2_A10;

-- Node name is ':20' = 'S3' 
-- Equation name is 'S3', location is LC7_A10, type is buried.
S3       = DFFE( _EQ007, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ007 =  EN & !_LC1_A10 &  S3
         #  EN &  _LC1_A10 & !S3;

-- Node name is ':19' = 'S4' 
-- Equation name is 'S4', location is LC4_A11, type is buried.
S4       = DFFE( _EQ008, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ008 =  EN & !_LC8_A10 &  S4
         #  EN &  _LC8_A10 & !S4;

-- Node name is ':18' = 'S5' 
-- Equation name is 'S5', location is LC3_A11, type is buried.
S5       = DFFE( _EQ009, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ009 =  EN & !S4 &  S5
         #  EN & !_LC8_A10 &  S5
         #  EN &  _LC8_A10 &  S4 & !S5;

-- Node name is '|LPM_ADD_SUB:113|addcore:adder|:71' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_A10', type is buried 
_LC1_A10 = LCELL( _EQ010);
  _EQ010 =  S0 &  S1 &  S2;

-- Node name is '|LPM_ADD_SUB:113|addcore:adder|:75' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_A10', type is buried 
_LC8_A10 = LCELL( _EQ011);
  _EQ011 =  _LC1_A10 &  S3;

-- Node name is ':4' 
-- Equation name is '_LC7_A4', type is buried 
_LC7_A4  = DFFE( STATE1, GLOBAL( CLK),  VCC,  VCC,  VCC);

-- Node name is ':6' 
-- Equation name is '_LC2_A4', type is buried 
_LC2_A4  = DFFE( _EQ012, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ012 =  STATE0 & !STATE1;

-- Node name is ':8' 
-- Equation name is '_LC1_A4', type is buried 
_LC1_A4  = DFFE( _EQ013, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ013 = !STATE0 & !STATE1;

-- Node name is ':10' 
-- Equation name is '_LC3_A4', type is buried 
_LC3_A4  = DFFE(!STATE1, GLOBAL( CLK),  VCC,  VCC,  VCC);

-- Node name is ':12' 
-- Equation name is '_LC6_A4', type is buried 
_LC6_A4  = DFFE( _EQ014, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ014 =  STATE0 &  STATE1;

-- Node name is ':14' 
-- Equation name is '_LC5_A4', type is buried 
_LC5_A4  = DFFE( _EQ015, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ015 = !STATE0 &  STATE1;

-- Node name is ':150' 
-- Equation name is '_LC4_A10', type is buried 
!_LC4_A10 = _LC4_A10~NOT;
_LC4_A10~NOT = LCELL( _EQ016);
  _EQ016 = !_LC1_A10 & !S3
         # !EN & !S3
         #  EN &  _LC1_A10 &  S3;

-- Node name is ':159' 
-- Equation name is '_LC2_A10', type is buried 
_LC2_A10 = LCELL( _EQ017);
  _EQ017 = !EN &  S2
         # !S0 &  S2
         # !S1 &  S2
         #  EN &  S0 &  S1 & !S2;

-- Node name is ':164' 
-- Equation name is '_LC2_A2', type is buried 
!_LC2_A2 = _LC2_A2~NOT;
_LC2_A2~NOT = LCELL( _EQ018);
  _EQ018 = !EN
         # !_LC2_A10;

-- Node name is '~212~1' 
-- Equation name is '~212~1', location is LC8_A11, type is buried.
-- synthesized logic cell 
_LC8_A11 = LCELL( _EQ019);
  _EQ019 = !EN
         # !S4 & !S5
         # !_LC8_A10 & !S5
         #  S4 &  S5
         # !_LC8_A10 &  S4
         #  _LC8_A10 & !S4;

-- Node name is ':212' 
-- Equation name is '_LC5_A11', type is buried 
!_LC5_A11 = _LC5_A11~NOT;
_LC5_A11~NOT = LCELL( _EQ020);
  _EQ020 = !_LC4_A10
         #  _LC6_A10
         #  _LC8_A11
         # !_LC2_A10;

-- Node name is ':291' 
-- Equation name is '_LC8_A5', type is buried 
_LC8_A5  = LCELL( _EQ021);
  _EQ021 =  SB & !SM
         #  _LC5_A11 &  SB;

-- Node name is ':309' 
-- Equation name is '_LC5_A5', type is buried 
_LC5_A5  = LCELL( _EQ022);
  _EQ022 = !_LC5_A11 &  SM
         # !SB;

-- Node name is '~329~1' 
-- Equation name is '~329~1', location is LC7_A11, type is buried.
-- synthesized logic cell 
_LC7_A11 = LCELL( _EQ023);
  _EQ023 =  S4 & !S5
         # !S4 &  S5
         # !_LC8_A10 &  S5
         # !EN &  S5
         # !_LC8_A10 &  S4
         #  EN &  _LC8_A10 & !S4
         # !EN &  S4;

-- Node name is ':329' 
-- Equation name is '_LC2_A11', type is buried 
!_LC2_A11 = _LC2_A11~NOT;
_LC2_A11~NOT = LCELL( _EQ024);
  _EQ024 =  _LC7_A11
         # !_LC2_A2
         #  _LC6_A10
         #  _LC4_A10;

-- Node name is '~404~1' 
-- Equation name is '~404~1', location is LC6_A11, type is buried.
-- synthesized logic cell 
_LC6_A11 = LCELL( _EQ025);
  _EQ025 = !S4 &  S5
         # !_LC8_A10 &  S5
         # !EN
         # !_LC8_A10 & !S4
         #  _LC8_A10 &  S4;

-- Node name is '~404~2' 
-- Equation name is '~404~2', location is LC6_A10, type is buried.
-- synthesized logic cell 
_LC6_A10 = LCELL( _EQ026);
  _EQ026 = !EN &  S1
         # !S0 &  S1
         # !EN & !S0
         #  EN &  S0;

-- Node name is ':404' 
-- Equation name is '_LC1_A11', type is buried 
!_LC1_A11 = _LC1_A11~NOT;
_LC1_A11~NOT = LCELL( _EQ027);
  _EQ027 =  _LC6_A11
         #  _LC2_A10
         # !_LC4_A10
         #  _LC6_A10;

-- Node name is ':483' 
-- Equation name is '_LC6_A5', type is buried 
_LC6_A5  = LCELL( _EQ028);
  _EQ028 =  _LC1_A11 &  SM
         # !SB;

-- Node name is ':501' 
-- Equation name is '_LC2_A5', type is buried 
_LC2_A5  = LCELL( _EQ029);
  _EQ029 = !_LC1_A11 &  SB
         #  SB & !SM;

-- Node name is ':684' 
-- Equation name is '_LC7_A5', type is buried 
_LC7_A5  = LCELL( _EQ030);
  _EQ030 =  _LC6_A5 & !STATE0 &  STATE1
         # !_LC2_A11 &  STATE0;

-- Node name is ':708' 
-- Equation name is '_LC3_A5', type is buried 
_LC3_A5  = LCELL( _EQ031);
  _EQ031 =  _LC2_A5 & !STATE0 &  STATE1
         # !_LC2_A11 &  STATE0;



Project Information                                d:\max2work\jtdkz\jtdkz.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10KA' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 10,873K

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