ymq.vhd

交通灯控制系统VHDL源码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY YMQ IS
  PORT(AIN4:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
       DOUT7:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END ENTITY YMQ;
 
ARCHITECTURE ART OF YMQ IS
  BEGIN 
  PROCESS(AIN4) IS
    BEGIN
    CASE AIN4 IS
    WHEN"0000"=>DOUT7<="0111111";
    WHEN"0001"=>DOUT7<="0000110";
    WHEN"0010"=>DOUT7<="1011011";
    WHEN"0011"=>DOUT7<="1001111";
    WHEN"0100"=>DOUT7<="1100110";
    WHEN"0101"=>DOUT7<="1101101";
    WHEN"0110"=>DOUT7<="1111101";
    WHEN"0111"=>DOUT7<="0000111";
    WHEN"1000"=>DOUT7<="1111111";
    WHEN"1001"=>DOUT7<="1101111";
    WHEN OTHERS=>DOUT7<="0000000";
    END CASE;
  END PROCESS;
END ARCHITECTURE ART;