📄 xskz.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY XSKZ IS
PORT(EN45,EN25,EN05M,EN05B:IN STD_LOGIC;
AIN45M,AIN45B,AIN25M,AIN25B,AIN05:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTM,DOUTB:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY XSKZ;
ARCHITECTURE ART OF XSKZ IS
BEGIN
PROCESS(EN45,EN25,EN05M,EN05B,AIN45M,AIN45B,AIN25M,AIN25B,AIN05) IS
BEGIN
IF EN45='1' THEN DOUTM<=AIN45M(7 DOWNTO 0);DOUTB<=AIN45B(7 DOWNTO 0);
ELSIF EN05M='1' THEN DOUTM<=AIN05(7 DOWNTO 0);DOUTB<=AIN05(7 DOWNTO 0);
ELSIF EN25='1' THEN DOUTM<=AIN25M(7 DOWNTO 0);DOUTB<=AIN25B(7 DOWNTO 0);
ELSIF EN05B='1' THEN DOUTM<=AIN05(7 DOWNTO 0);DOUTB<=AIN05(7 DOWNTO 0);
END IF;
END PROCESS;
END ARCHITECTURE ART;
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