📄 cnt05s.rpt
字号:
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\max2work\jtdkz\cnt05s.rpt
cnt05s
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - A 03 AND2 s 2 0 0 3 EN05M~1
- 7 - A 03 DFFE + 0 3 0 3 CNT3B2 (:12)
- 6 - A 03 DFFE + 0 2 0 4 CNT3B1 (:13)
- 4 - A 03 DFFE + 0 1 0 3 CNT3B0 (:14)
- 3 - A 03 AND2 0 2 1 0 :464
- 1 - A 03 AND2 0 2 1 0 :484
- 5 - A 03 OR2 0 3 1 0 :500
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\max2work\jtdkz\cnt05s.rpt
cnt05s
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\max2work\jtdkz\cnt05s.rpt
cnt05s
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 3 CLK
Device-Specific Information: d:\max2work\jtdkz\cnt05s.rpt
cnt05s
** EQUATIONS **
CLK : INPUT;
EN05B : INPUT;
EN05M : INPUT;
-- Node name is ':14' = 'CNT3B0'
-- Equation name is 'CNT3B0', location is LC4_A3, type is buried.
CNT3B0 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = !CNT3B0
# _LC2_A3;
-- Node name is ':13' = 'CNT3B1'
-- Equation name is 'CNT3B1', location is LC6_A3, type is buried.
CNT3B1 = DFFE( _EQ002, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = _LC2_A3
# CNT3B0 & !CNT3B1
# !CNT3B0 & CNT3B1;
-- Node name is ':12' = 'CNT3B2'
-- Equation name is 'CNT3B2', location is LC7_A3, type is buried.
CNT3B2 = DFFE( _EQ003, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = !CNT3B0 & CNT3B2
# !CNT3B1 & CNT3B2
# CNT3B0 & CNT3B1 & !CNT3B2
# _LC2_A3;
-- Node name is 'DOUT50'
-- Equation name is 'DOUT50', type is output
DOUT50 = _LC5_A3;
-- Node name is 'DOUT51'
-- Equation name is 'DOUT51', type is output
DOUT51 = _LC1_A3;
-- Node name is 'DOUT52'
-- Equation name is 'DOUT52', type is output
DOUT52 = _LC3_A3;
-- Node name is 'DOUT53'
-- Equation name is 'DOUT53', type is output
DOUT53 = GND;
-- Node name is 'DOUT54'
-- Equation name is 'DOUT54', type is output
DOUT54 = GND;
-- Node name is 'DOUT55'
-- Equation name is 'DOUT55', type is output
DOUT55 = GND;
-- Node name is 'DOUT56'
-- Equation name is 'DOUT56', type is output
DOUT56 = GND;
-- Node name is 'DOUT57'
-- Equation name is 'DOUT57', type is output
DOUT57 = GND;
-- Node name is 'EN05M~1'
-- Equation name is 'EN05M~1', location is LC2_A3, type is buried.
-- synthesized logic cell
_LC2_A3 = LCELL( _EQ004);
_EQ004 = !EN05B & !EN05M;
-- Node name is ':464'
-- Equation name is '_LC3_A3', type is buried
_LC3_A3 = LCELL( _EQ005);
_EQ005 = !CNT3B1 & !CNT3B2;
-- Node name is ':484'
-- Equation name is '_LC1_A3', type is buried
_LC1_A3 = LCELL( _EQ006);
_EQ006 = CNT3B1 & !CNT3B2;
-- Node name is ':500'
-- Equation name is '_LC5_A3', type is buried
_LC5_A3 = LCELL( _EQ007);
_EQ007 = !CNT3B0 & !CNT3B2
# !CNT3B0 & !CNT3B1;
Project Information d:\max2work\jtdkz\cnt05s.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10KA' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,005K
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