control.v

是一个用于soc的32bit risc核

			11'b1_10111010_01:  state <= InstrExec;
			11'b1_10111011_01:  state <= InstrExec;
			11'b1_10111100_01:  state <= InstrExec;
			11'b1_10111101_01:  state <= InstrExec;
			11'b1_10111110_01:  state <= InstrExec;
			11'b1_10111111_01:  state <= InstrExec;
			11'b1_11000000_01:  state <= InstrExec;
			11'b1_11000001_01:  state <= InstrExec;
			11'b1_11000010_01:  state <= InstrExec;
			11'b1_11000011_01:  state <= InstrExec;
			11'b1_11000100_01:  state <= InstrExec;
			11'b1_11000101_01:  state <= InstrExec;
			11'b1_11000110_01:  state <= InstrExec;
			11'b1_11000111_01:  state <= InstrExec;
			11'b1_11001000_01:  state <= InstrExec;
			11'b1_11001001_01:  state <= InstrExec;
			11'b1_11001010_01:  state <= InstrExec;
			11'b1_11001011_01:  state <= InstrExec;
			11'b1_11001100_01:  state <= InstrExec;
			11'b1_11001101_01:  state <= InstrExec;
			11'b1_11001110_01:  state <= InstrExec;
			11'b1_11001111_01:  state <= InstrExec;
			11'b1_11010000_01:  state <= InstrExec;
			11'b1_11010001_01:  state <= InstrExec;
			11'b1_11010010_01:  state <= InstrExec;
			11'b1_11010011_01:  state <= InstrExec;
			11'b1_11010100_01:  state <= InstrExec;
			11'b1_11010101_01:  state <= InstrExec;
			11'b1_11010110_01:  state <= InstrExec;
			11'b1_11010111_01:  state <= InstrExec;
			11'b1_11011000_01:  state <= InstrExec;
			11'b1_11011001_01:  state <= InstrExec;
			11'b1_11011010_01:  state <= InstrExec;
			11'b1_11011011_01:  state <= InstrExec;
			11'b1_11011100_01:  state <= InstrExec;
			11'b1_11011101_01:  state <= InstrExec;
			11'b1_11011110_01:  state <= InstrExec;
			11'b1_11011111_01:  state <= InstrExec;
			11'b1_11100000_01:  state <= InstrExec;
			11'b1_11100001_01:  state <= InstrExec;
			11'b1_11100010_01:  state <= InstrExec;
			11'b1_11100011_01:  state <= InstrExec;
			11'b1_11100100_01:  state <= InstrExec;
			11'b1_11100101_01:  state <= InstrExec;
			11'b1_11100110_01:  state <= InstrExec;
			11'b1_11100111_01:  state <= InstrExec;
			11'b1_11101000_01:  state <= InstrExec;
			11'b1_11101001_01:  state <= InstrExec;
			11'b1_11101010_01:  state <= InstrExec;
			11'b1_11101011_01:  state <= InstrExec;
			11'b1_11101100_01:  state <= InstrExec;
			11'b1_11101101_01:  state <= InstrExec;
			11'b1_11101110_01:  state <= InstrExec;
			11'b1_11101111_01:  state <= InstrExec;
			11'b1_11110000_01:  state <= InstrExec;
			11'b1_11110001_01:  state <= InstrExec;
			11'b1_11110010_01:  state <= InstrExec;
			11'b1_11110011_01:  state <= InstrExec;
			11'b1_11110100_01:  state <= InstrExec;
			11'b1_11110101_01:  state <= InstrExec;
			11'b1_11110110_01:  state <= InstrExec;
			11'b1_11110111_01:  state <= InstrExec;
			11'b1_11111000_01:  state <= InstrExec;
			11'b1_11111001_01:  state <= InstrExec;
			11'b1_11111010_01:  state <= InstrExec;
			11'b1_11111011_01:  state <= InstrExec;
			11'b1_11111100_01:  state <= InstrExec;
			11'b1_11111101_01:  state <= InstrExec;
			11'b1_11111110_01:  state <= InstrExec;
			11'b1_11111111_01:  state <= InstrExec;
			11'b1_00000111_10:  state <= InstrStop;
			11'b1_xxxxxxxx_10:  state <= InstrFetch;
			11'b1_00000111_11:  state <= Init;
			default:			     state <= Init;
		endcase
	end
end


// Finite State Machine's Combinatorial Section
always @(reset or state or ACCNeg or ACCZero or OpCode)
begin
	if (reset == 1'b1)
	begin
		PCInEn 		<= Low;
		IRInEn 		<= Low;
		ACCInEn 		<= Low;
		ACCOutEn 	<= Low;
		MemReq 		<= Low;
		RdWrBar 		<= Low;
		AddressSel 	<= Low;
		ALUSrcBSel 	<= Low;
	end
	else
	if (state == InstrFetch)
	begin
	   PCInEn 		<= High;
		IRInEn 		<= High;
		ACCInEn 		<= Low;
		ACCOutEn 	<= Low;
	   MemReq 		<= High;
		RdWrBar 		<= High;
		AddressSel 	<= SelInstrAddr;
	   ALUSrcBSel 	<= SelAddress;
	end
	else
 	if (state == InstrExec)
	begin
    case (OpCode)
   
	 LDA:
  		begin
        PCInEn 		<= Low;
		  IRInEn 		<= Low;
		  ACCInEn 		<= High;
		  ACCOutEn 		<= Low;
        MemReq 		<= High;
		  RdWrBar 		<= High;
		  AddressSel 	<= SelOperandAddr;
        ALUSrcBSel 	<= SelData;
      end
    STO:
    	begin
        PCInEn <= Low;
		  IRInEn <= Low;
		  ACCInEn <= Low;
		  ACCOutEn <= High;
        MemReq <= High;
		  RdWrBar <= Low;
		  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelAddress;
      end
    ADD:
	 	begin
        PCInEn <= Low;
		  IRInEn <= Low;
		  ACCInEn <= High;
		  ACCOutEn <= Low;
        MemReq <= High;
		  RdWrBar <= High;
		  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelData;
       end
    SUB:
    	begin
        PCInEn <= Low;
		  IRInEn <= Low;
		  ACCInEn <= High;
		  ACCOutEn <= Low;
        MemReq <= High;
		  RdWrBar <= High;
		  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelData;
      end
    JMP:
    	begin
        PCInEn <= High;
		  IRInEn <= Low;
		  ACCInEn <= Low;
		  ACCOutEn <= Low;
        MemReq <= Low;
		  RdWrBar <= High;
		  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelAddress;
      end
    JGE:
    	begin
        PCInEn <= ~ACCNeg;
		  IRInEn <= Low;
		  ACCInEn <= Low;
		  ACCOutEn <= Low;
        MemReq <= Low;
		  RdWrBar <= High;
		  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelAddress;
      end
    JNE:
    	begin
        PCInEn <= ~ACCZero;
		  IRInEn <= Low;
		  ACCInEn <= Low;
		  ACCOutEn <= Low;
        MemReq <= Low;
		  RdWrBar <= High;
		  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelAddress;
      end
    STP:
	 	begin
        PCInEn <= Low;
		  IRInEn <= Low;
		  ACCInEn <= Low;
		  ACCOutEn <= Low;
        MemReq <= Low;
		  RdWrBar <= High;
		  AddressSel <= SelAddress;
        ALUSrcBSel <= SelAddress;
	   end
    SHR:
	 	begin
        PCInEn <= Low;
		  IRInEn <= Low;
		  ACCInEn <= High;
		  ACCOutEn <= Low;
        MemReq <= Low;
		  RdWrBar <= Low;
		  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelAddress;
	   end
    SHL:
	 	begin
        PCInEn <= Low;
		  IRInEn <= Low;
		  ACCInEn <= High;
		  ACCOutEn <= Low;
        MemReq <= Low;
		  RdWrBar <= Low;
		  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelAddress;
   	end
    AND:
	 	begin
        PCInEn <= Low;
		  IRInEn <= Low;
		  ACCInEn <= High;
		  ACCOutEn <= Low;
        MemReq <= High;
		  RdWrBar <= High;
		  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelData;
   	end
    OR:
	 	begin
        PCInEn <= Low;
		  IRInEn <= Low;
		  ACCInEn <= High;
		  ACCOutEn <= Low;
        MemReq <= High;
		  RdWrBar <= High;
		  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelData;
   	end
    XOR:
	 	begin
        PCInEn <= Low;
		  IRInEn <= Low;
		  ACCInEn <= High;
		  ACCOutEn <= Low;
        MemReq <= High;
		  RdWrBar <= High;
		  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelData;
   	end
    COM:
	 	begin
        PCInEn <= Low;
		  IRInEn <= Low;
		  ACCInEn <= High;
		  ACCOutEn <= Low;
        MemReq <= High;
		  RdWrBar <= High;
		  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelData;
   	end
    SWP:
	 	begin
        PCInEn <= Low;
		  IRInEn <= Low;
		  ACCInEn <= High;
		  ACCOutEn <= Low;
        MemReq <= High;
		  RdWrBar <= High;
		  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelData;
   	end
    NOP:
	 	begin
        PCInEn <= Low;
		  IRInEn <= Low;
		  ACCInEn <= Low;
		  ACCOutEn <= Low;
        MemReq <= Low;
		  RdWrBar <= High;
		  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelAddress;
   	end
    default:
	 	begin
        PCInEn <= Low;
		  IRInEn <= Low;
		  ACCInEn <= Low;
		  ACCOutEn <= Low;
        MemReq <= Low;
		  RdWrBar <= High;
		  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelAddress;
      end
    endcase
	 end
	else
 	if (state == InstrStop)
   begin
       PCInEn <= Low;
		 IRInEn <= Low;
		 ACCInEn <= Low;
		 ACCOutEn <= Low;
       MemReq <= Low;
		 RdWrBar <= High;
		 AddressSel <= SelAddress;
       ALUSrcBSel <= SelAddress;
   end
end
endmodule