opensparc ddr2 controller rtl files.v

基于FPGA的DDR2控制程序

        .rst_l  (~writeqbank0vld5reset_arb),
        .en     (wqb0entry5wren),
        .clk    (clk));

dffrle_ns writeqbank0vld6flop_arb (
        .din    (1'b1),
        .q      (writeqbank0vld6_arb),
        .rst_l  (~writeqbank0vld6reset_arb),
        .en     (wqb0entry6wren),
        .clk    (clk));

dffrle_ns writeqbank0vld7flop_arb (
        .din    (1'b1),
        .q      (writeqbank0vld7_arb),
        .rst_l  (~writeqbank0vld7reset_arb),
        .en     (wqb0entry7wren),
        .clk    (clk));

// Valids for new write request allocation only. 

dffrle_ns writeqbank0vld0flop (
        .din    (1'b1),
        .q      (writeqbank0vld0),
        .rst_l  (~writeqbank0vld0reset),
        .en     (wqb0entry0wren),
        .clk    (clk));

dffrle_ns writeqbank0vld1flop (
        .din    (1'b1),
        .q      (writeqbank0vld1),
        .rst_l  (~writeqbank0vld1reset),
        .en     (wqb0entry1wren),
        .clk    (clk));

dffrle_ns writeqbank0vld2flop (
        .din    (1'b1),
        .q      (writeqbank0vld2),
        .rst_l  (~writeqbank0vld2reset),
        .en     (wqb0entry2wren),
        .clk    (clk));

dffrle_ns writeqbank0vld3flop (
        .din    (1'b1),
        .q      (writeqbank0vld3),
        .rst_l  (~writeqbank0vld3reset),
        .en     (wqb0entry3wren),
        .clk    (clk));

dffrle_ns writeqbank0vld4flop (
        .din    (1'b1),
        .q      (writeqbank0vld4),
        .rst_l  (~writeqbank0vld4reset),
        .en     (wqb0entry4wren),
        .clk    (clk));

dffrle_ns writeqbank0vld5flop (
        .din    (1'b1),
        .q      (writeqbank0vld5),
        .rst_l  (~writeqbank0vld5reset),
        .en     (wqb0entry5wren),
        .clk    (clk));

dffrle_ns writeqbank0vld6flop (
        .din    (1'b1),
        .q      (writeqbank0vld6),
        .rst_l  (~writeqbank0vld6reset),
        .en     (wqb0entry6wren),
        .clk    (clk));

dffrle_ns writeqbank0vld7flop (
        .din    (1'b1),
        .q      (writeqbank0vld7),
        .rst_l  (~writeqbank0vld7reset),
        .en     (wqb0entry7wren),
        .clk    (clk));

// Address 

dffe_ns  #(36) writeqbank0entry0flop (
        .din    (que_wr_addr0[35:0]),
        .q      (writeqbank0addr0[35:0]), 
        .en     (wqb0entry0wren),
        .clk    (clk));

dffe_ns  #(36) writeqbank0entry1flop (
        .din    (que_wr_addr0[35:0]),
        .q      (writeqbank0addr1[35:0]),
        .en     (wqb0entry1wren),
        .clk    (clk));

dffe_ns  #(36) writeqbank0entry2flop (
        .din    (que_wr_addr0[35:0]),
        .q      (writeqbank0addr2[35:0]),
        .en     (wqb0entry2wren),
        .clk    (clk));

dffe_ns  #(36) writeqbank0entry3flop (
        .din    (que_wr_addr0[35:0]),
        .q      (writeqbank0addr3[35:0]),
        .en     (wqb0entry3wren),
        .clk    (clk));

dffe_ns  #(36) writeqbank0entry4flop (
        .din    (que_wr_addr0[35:0]),
        .q      (writeqbank0addr4[35:0]),
        .en     (wqb0entry4wren),
        .clk    (clk));

dffe_ns  #(36) writeqbank0entry5flop (
        .din    (que_wr_addr0[35:0]),
        .q      (writeqbank0addr5[35:0]),
        .en     (wqb0entry5wren),
        .clk    (clk));

dffe_ns  #(36) writeqbank0entry6flop (
        .din    (que_wr_addr0[35:0]),
        .q      (writeqbank0addr6[35:0]),
        .en     (wqb0entry6wren),
        .clk    (clk));

dffe_ns  #(36) writeqbank0entry7flop (
        .din    (que_wr_addr0[35:0]),
        .q      (writeqbank0addr7[35:0]),
        .en     (wqb0entry7wren),
        .clk    (clk));

// Data write address
dffe_ns  #(3) writeqentry0flop (
        .din    (que_cpu_wr_addr[2:0]),
        .q      (writeqaddr0[2:0]), 
        .en     (wqb0entry0wren),
        .clk    (clk));

dffe_ns  #(3) writeqentry1flop (
        .din    (que_cpu_wr_addr[2:0]),
        .q      (writeqaddr1[2:0]),
        .en     (wqb0entry1wren),
        .clk    (clk));

dffe_ns  #(3) writeqentry2flop (
        .din    (que_cpu_wr_addr[2:0]),
        .q      (writeqaddr2[2:0]),
        .en     (wqb0entry2wren),
        .clk    (clk));

dffe_ns  #(3) writeqentry3flop (
        .din    (que_cpu_wr_addr[2:0]),
        .q      (writeqaddr3[2:0]),
        .en     (wqb0entry3wren),
        .clk    (clk));

dffe_ns  #(3) writeqentry4flop (
        .din    (que_cpu_wr_addr[2:0]),
        .q      (writeqaddr4[2:0]),
        .en     (wqb0entry4wren),
        .clk    (clk));

dffe_ns  #(3) writeqentry5flop (
        .din    (que_cpu_wr_addr[2:0]),
        .q      (writeqaddr5[2:0]),
        .en     (wqb0entry5wren),
        .clk    (clk));

dffe_ns  #(3) writeqentry6flop (
        .din    (que_cpu_wr_addr[2:0]),
        .q      (writeqaddr6[2:0]),
        .en     (wqb0entry6wren),
        .clk    (clk));

dffe_ns  #(3) writeqentry7flop (
        .din    (que_cpu_wr_addr[2:0]),
        .q      (writeqaddr7[2:0]),
        .en     (wqb0entry7wren),
        .clk    (clk));

//////////////////////////////////////////////////////////////////
// Creating collapsing(??? Do we need it to be) fifo. This contains
// read and write queue id and a valid bit for one bank. This is
// because there could be a reads/write to the diff banks simultaneously.
// Reads are placed into 0-3 of the queue  and writes 4-7.
//////////////////////////////////////////////////////////////////

wire            que_b0_wr_index_en;
wire [8:0]      que_b0_wr_index_ent0;
wire [8:0]	que_b0_wr_index_ent1;
wire [8:0]	que_b0_wr_index_ent2;
wire [8:0]	que_b0_wr_index_ent3;
wire [8:0]      que_b0_wr_index_ent4;
wire [8:0]	que_b0_wr_index_ent5;
wire [8:0]	que_b0_wr_index_ent6;
wire [8:0]	que_b0_wr_index_ent7;
wire		que_ras_bank_picked_en;
wire		que_b0_wr_picked;
wire           	que_b0_index1_en_d1;
wire           	que_b0_index2_en_d1;
wire           	que_b0_index3_en_d1;
wire           	que_b0_index4_en_d1;
wire           	que_b0_index5_en_d1;
wire           	que_b0_index6_en_d1;
wire           	que_b0_index7_en_d1;
wire           	que_b0_wr_index1_en_d1;
wire           	que_b0_wr_index2_en_d1;
wire           	que_b0_wr_index3_en_d1;
wire           	que_b0_wr_index4_en_d1;
wire           	que_b0_wr_index5_en_d1;
wire           	que_b0_wr_index6_en_d1;
wire           	que_b0_wr_index7_en_d1;

reg            	que_b0_index0_en;
reg            	que_b0_index1_en;
reg            	que_b0_index2_en;
reg            	que_b0_index3_en;
reg            	que_b0_index4_en;
reg            	que_b0_index5_en;
reg            	que_b0_index6_en;
reg            	que_b0_index7_en;
reg            	que_b0_wr_index0_en;
reg            	que_b0_wr_index1_en;
reg            	que_b0_wr_index2_en;
reg            	que_b0_wr_index3_en;
reg            	que_b0_wr_index4_en;
reg            	que_b0_wr_index5_en;
reg            	que_b0_wr_index6_en;
reg            	que_b0_wr_index7_en;
reg            	que_b0_index0_val_in;
reg            	que_b0_index1_val_in;
reg            	que_b0_index2_val_in;
reg            	que_b0_index3_val_in;
reg            	que_b0_index4_val_in;
reg            	que_b0_index5_val_in;
reg            	que_b0_index6_val_in;
reg            	que_b0_index7_val_in;
reg            	que_b0_wr_index0_val_in;
reg            	que_b0_wr_index1_val_in;
reg            	que_b0_wr_index2_val_in;
reg            	que_b0_wr_index3_val_in;
reg            	que_b0_wr_index4_val_in;
reg            	que_b0_wr_index5_val_in;
reg            	que_b0_wr_index6_val_in;
reg            	que_b0_wr_index7_val_in;

wire que_this_channel_picked_d1 = (que_channel_picked_internal_d1 == que_channel_disabled);
      
wire que_rd_ras_picked_d1 = ~que_scrb_picked_d1 & (~que_b0_wr_index_pend_d1 & que_b0_rd_picked_d1) &
                        que_this_channel_picked_d1 & (|que_ras_picked_d1[7:0]);

dff_ns  #(2) 	ras_picked_d2 (
        .din    ({que_b0_index_en, que_rd_ras_picked_d1}),
        .q      ({que_b0_index_en_d1, que_rd_ras_picked_d2}),
        .clk    (clk));

// collapsing queue for READS
assign que_b0_rdq_full =  readqbank0vld7 & readqbank0vld6 & readqbank0vld5 & readqbank0vld4 &
			readqbank0vld3 & readqbank0vld2 & readqbank0vld1 & readqbank0vld0;
assign que_b0_rd_index[7:0] = {que_rd_addr0[35], que_rd_addr0[33], que_rd_addr_in[2:0], que_rd_addr0[2:0]};

// set and reset the valids in this queue
assign que_b0_index_en = (que_rd_req & ~que_b0_rdq_full) & ~(que_ras_bank_picked_en & 
			(que_channel_picked_internal == que_channel_disabled) &
			~(que_scrb_picked | que_b0_rd_picked | que_b0_wr_picked) ) ;

always @(/*AUTOSENSE*/que_b0_index1_en_d1 or que_b0_index2_en_d1
	 or que_b0_index3_en_d1 or que_b0_index4_en_d1
	 or que_b0_index5_en_d1 or que_b0_index6_en_d1
	 or que_b0_index7_en_d1 or que_b0_index_en or que_b0_index_en_d1
	 or que_b0_index_ent0 or que_b0_index_ent1
	 or que_b0_index_ent2 or que_b0_index_ent3
	 or que_b0_index_ent4 or que_b0_index_ent5
	 or que_b0_index_ent6 or que_b0_index_ent7
	 or que_b0_indx0_val_d1 or que_b0_indx1_val_d1
	 or que_b0_indx2_val_d1 or que_b0_indx3_val_d1
	 or que_b0_indx4_val_d1 or que_b0_indx5_val_d1
	 or que_b0_indx6_val_d1 or que_b0_indx7_val_d1
	 or que_b0_rd_picked_d1 or que_b0_wr_index_pend_d1
	 or que_ras_picked_d1 or que_scrb_picked_d1
	 or que_this_channel_picked_d1 or que_rd_ras_picked_d2) 
begin
	que_b0_index0_en = 1'h0;
	que_b0_index1_en = 1'h0;
	que_b0_index2_en = 1'h0;
	que_b0_index3_en = 1'h0;
	que_b0_index4_en = 1'h0;
	que_b0_index5_en = 1'h0;
	que_b0_index6_en = 1'h0;
	que_b0_index7_en = 1'h0;
	que_b0_index7_val_in = que_b0_index_ent7[6];
	que_b0_index6_val_in = que_b0_index_ent6[6];
	que_b0_index5_val_in = que_b0_index_ent5[6];
	que_b0_index4_val_in = que_b0_index_ent4[6];
	que_b0_index3_val_in = que_b0_index_ent3[6];
	que_b0_index2_val_in = que_b0_index_ent2[6];
	que_b0_index1_val_in = que_b0_index_ent1[6];
	que_b0_index0_val_in = que_b0_index_ent0[6];

	// If not scrub & its not a write and a read & this channel req
	// got picked in two channel mode & ras_picked is non zero & 
	// (the valids present match to the ras picked or when a new req came in
	//  and pushed the current picked down by one) 

	if(~que_scrb_picked_d1 & (~que_b0_wr_index_pend_d1 & que_b0_rd_picked_d1) & 
			que_this_channel_picked_d1 & (|que_ras_picked_d1) &
                        (que_b0_indx7_val_d1[7:0] == que_ras_picked_d1[7:0] |
			(~que_rd_ras_picked_d2 | que_b0_index_en_d1 & que_rd_ras_picked_d2) &
			 que_b0_index7_en_d1 & (que_b0_indx6_val_d1 == que_ras_picked_d1)))
        begin
                que_b0_index7_en = 1'h1;
                que_b0_index7_val_in = 1'h0;
                if(que_b0_index_en) 
                begin
                        que_b0_index7_en = 1'h1;
                        que_b0_index6_en = 1'h1;
                        que_b0_index5_en = 1'h1;
                        que_b0_index4_en = 1'h1;
                        que_b0_index3_en = 1'h1;
                        que_b0_index2_en = 1'h1;
                        que_b0_index1_en = 1'h1;
                        que_b0_index0_en = 1'h1;
                        que_b0_index7_val_in = que_b0_index_ent6[6];
                        que_b0_index6_val_in = que_b0_index_ent5[6];
                        que_b0_index5_val_in = que_b0_index_ent4[6];
                        que_b0_index4_val_in = que_b0_index_ent3[6];
                        que_b0_index3_val_in = que_b0_index_ent2[6];
                        que_b0_index2_val_in = que_b0_index_ent1[6];
                        que_b0_index1_val_in = que_b0_index_ent0[6];
                        que_b0_index0_val_in = 1'h1;
                end
        end
	else if(~que_scrb_picked_d1 & (~que_b0_wr_index_pend_d1 & que_b0_rd_picked_d1) & 
			que_this_channel_picked_d1 & (|que_ras_picked_d1) &
                        (que_b0_indx6_val_d1[7:0] == que_ras_picked_d1[7:0] |
			(~que_rd_ras_picked_d2 | que_b0_index_en_d1 & que_rd_ras_picked_d2) &
			 que_b0_index6_en_d1 & (que_b0_indx5_val_d1 == que_ras_picked_d1)))
        begin
                que_b0_index6_en = 1'h1;
                que_b0_index6_val_in = 1'h0;
                if(que_b0_index_en) 
                begin
                        que_b0_index6_en = 1'h1;
                        que_b0_index5_en = 1'h1;
                        que_b0_index4_en = 1'h1;
                        que_b0_index3_en = 1'h1;
                        que_b0_index2_en = 1'h1;
                        que_b0_index1_en = 1'h1;
                        que_b0_index0_en = 1'h1;
                        que_b0_index6_val_in = que_b0_index_ent5[6];
                        que_b0_index5_val_in = que_b0_index_ent4[6];
                        que_b0_index4_val_in = que_b0_index_ent3[6];
                        que_b0_index3_val_in = que_b0_index_ent2[6];
                        que_b0_index2_val_in = que_b0_index_ent1[6];
                        que_b0_index1_val_in = que_b0_index_ent0[6];
                        que_b0_index0_val_in = 1'h1;
                end     
        end
	else if(~que_scrb_picked_d1 & (~que_b0_wr_index_pend_d1 & que_b0_rd_picked_d1) & 
			que_this_channel_picked_d1 & (|que_ras_picked_d1) &
                        (que_b0_indx5_val_d1[7:0] == que_ras_picked_d1[7:0] |
			(~que_rd_ras_picked_d2 | que_b0_index_en_d1 & que_rd_ras_picked_d2) &
			 que_b0_index5_en_d1 & (que_b0_indx4_val_d1 == que_ras_picked_d1)))
        begin
                que_b0_index5_en = 1'h1;
                que_b0_index5_val_in = 1'h0;
                if(que_b0_index_en) 
                begin
                        que_b0_index5_en = 1'h1;
                        que_b0_index4_en = 1'h1;