opensparc ddr2 controller rtl files.v

基于FPGA的DDR2控制程序

        .clk    (clk));

//////////////////////////////////////////////////////////////////
// write index 
//////////////////////////////////////////////////////////////////
wire [2:0]	que_rd_addr_in;

assign que_wr_addr_b0 = {wqb0entry4wren|wqb0entry5wren|wqb0entry6wren|wqb0entry7wren, 
			wqb0entry7wren|wqb0entry6wren|wqb0entry3wren|wqb0entry2wren, 
			wqb0entry7wren|wqb0entry5wren|wqb0entry3wren|wqb0entry1wren};
assign que_rd_addr_in = {rqb0entry4wren|rqb0entry5wren|rqb0entry6wren|rqb0entry7wren, 
			rqb0entry7wren|rqb0entry6wren|rqb0entry3wren|rqb0entry2wren, 
			rqb0entry7wren|rqb0entry5wren|rqb0entry3wren|rqb0entry1wren};

//////////////////////////////////////////////////////////////////
// Write into the Read Queue's (Pick one empty entry)
//////////////////////////////////////////////////////////////////

assign rqb0entry0wren =  ~readqbank0vld0 & que_rd_req; 
assign rqb0entry1wren =  ~readqbank0vld1 & readqbank0vld0 & 
				que_rd_req;
assign rqb0entry2wren =  ~readqbank0vld2 & readqbank0vld1 & readqbank0vld0 & 
				que_rd_req; 
assign rqb0entry3wren =  ~readqbank0vld3 & readqbank0vld2 & readqbank0vld1 & 
				readqbank0vld0 & que_rd_req; 
assign rqb0entry4wren =  ~readqbank0vld4 & readqbank0vld3 & readqbank0vld2 & readqbank0vld1 &
                        	readqbank0vld0 & que_rd_req;
assign rqb0entry5wren =  ~readqbank0vld5 & readqbank0vld4 & readqbank0vld3 & readqbank0vld2 & 
				readqbank0vld1 & readqbank0vld0 & que_rd_req;
assign rqb0entry6wren =  ~readqbank0vld6 & readqbank0vld5 & readqbank0vld4 & readqbank0vld3 & 
				readqbank0vld2 & readqbank0vld1 & readqbank0vld0 & que_rd_req;
assign rqb0entry7wren =  ~readqbank0vld7 & readqbank0vld6 & readqbank0vld5 & readqbank0vld4 & 
				readqbank0vld3 & readqbank0vld2 & readqbank0vld1 & readqbank0vld0 & 
				que_rd_req;

//////////////////////////////////////////////////////////////////
// Write into the Write Queue's (Pick one valid entry)
//////////////////////////////////////////////////////////////////

// Silently drop req if address is out of range. so AND it with bit 32 of address.

assign wqb0entry0wren =  ~writeqbank0vld0 & que_wr_req & ~que_wr_addr0[32];
assign wqb0entry1wren =  ~writeqbank0vld1 & writeqbank0vld0 & 
				que_wr_req & ~que_wr_addr0[32]; 
assign wqb0entry2wren =  ~writeqbank0vld2 & writeqbank0vld1 & writeqbank0vld0 & 
				que_wr_req & ~que_wr_addr0[32]; 
assign wqb0entry3wren =  ~writeqbank0vld3 & writeqbank0vld2 & writeqbank0vld1 & 
				writeqbank0vld0 & que_wr_req & ~que_wr_addr0[32];
assign wqb0entry4wren =  ~writeqbank0vld4 & writeqbank0vld3 & writeqbank0vld2 & writeqbank0vld1 &
                        	writeqbank0vld0 & que_wr_req & ~que_wr_addr0[32];
assign wqb0entry5wren =  ~writeqbank0vld5 & writeqbank0vld4 & writeqbank0vld3 & writeqbank0vld2 & 
				writeqbank0vld1 & writeqbank0vld0 & que_wr_req & ~que_wr_addr0[32];
assign wqb0entry6wren =  ~writeqbank0vld6 & writeqbank0vld5 & writeqbank0vld4 & writeqbank0vld3 & 
				writeqbank0vld2 & writeqbank0vld1 & writeqbank0vld0 & 
				que_wr_req & ~que_wr_addr0[32];
assign wqb0entry7wren =  ~writeqbank0vld7 & writeqbank0vld6 & writeqbank0vld5 & writeqbank0vld4 & 
				writeqbank0vld3 & writeqbank0vld2 & writeqbank0vld1 & 
				writeqbank0vld0 & que_wr_req & ~que_wr_addr0[32];

//////////////////////////////////////////////////////////////////
//// Read Queues for 1 banks of L2 (1 DRAM channel)
//////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////
// Read Request Address bits and ID for bank0 
//////////////////////////////////////////////////////////////////

// Stage these so that reset happens 1 cycle later then the request got picked
dff_ns #(5) ff_cmd_picked(
        .din    ({que_channel_picked_internal, que_b0_cmd_picked, que_b0_index_picked[2:0]}),
        .q      ({que_channel_picked_internal_d1, que_b0_cmd_picked_d1, 
			que_b0_index_picked_d1[2:0]}),
        .clk    (clk));

// Generate read picked - it is ANDed due to rd is not always high priority
wire que_b0_rd_picked_in = que_b0_rd_picked & ~que_b0_cmd_picked & 
					(que_channel_picked_internal == que_channel_disabled);

dff_ns  #(4) ff_index_en (
        .din    ({que_cmd_picked, que_scrb_picked, que_b0_wr_index_pend, que_b0_rd_picked_in}),
        .q    	({que_cmd_picked_d1, que_scrb_picked_d1, que_b0_wr_index_pend_d1, que_b0_rd_picked_d1}),
        .clk    (clk));

assign readqbank0vld0reset = ~rst_l | (({que_b0_cmd_picked_d1,que_b0_index_picked_d1} == 4'h0) & 
					~que_scrb_picked_d1 & |que_ras_picked_d1[7:0] &
					(que_channel_picked_internal_d1 == que_channel_disabled));
assign readqbank0vld1reset = ~rst_l | (({que_b0_cmd_picked_d1,que_b0_index_picked_d1} == 4'h1) & 
					~que_scrb_picked_d1 & |que_ras_picked_d1[7:0] &
					(que_channel_picked_internal_d1 == que_channel_disabled));
assign readqbank0vld2reset = ~rst_l | (({que_b0_cmd_picked_d1,que_b0_index_picked_d1} == 4'h2) & 
					~que_scrb_picked_d1 & |que_ras_picked_d1[7:0] &
					(que_channel_picked_internal_d1 == que_channel_disabled));
assign readqbank0vld3reset = ~rst_l | (({que_b0_cmd_picked_d1,que_b0_index_picked_d1} == 4'h3) & 
					~que_scrb_picked_d1 & |que_ras_picked_d1[7:0] &
					(que_channel_picked_internal_d1 == que_channel_disabled));
assign readqbank0vld4reset = ~rst_l | (({que_b0_cmd_picked_d1,que_b0_index_picked_d1} == 4'h4) & 
					~que_scrb_picked_d1 & |que_ras_picked_d1[7:0] &
					(que_channel_picked_internal_d1 == que_channel_disabled));
assign readqbank0vld5reset = ~rst_l | (({que_b0_cmd_picked_d1,que_b0_index_picked_d1} == 4'h5) & 
					~que_scrb_picked_d1 & |que_ras_picked_d1[7:0] &
					(que_channel_picked_internal_d1 == que_channel_disabled));
assign readqbank0vld6reset = ~rst_l | (({que_b0_cmd_picked_d1,que_b0_index_picked_d1} == 4'h6) & 
					~que_scrb_picked_d1 & |que_ras_picked_d1[7:0] &
					(que_channel_picked_internal_d1 == que_channel_disabled));
assign readqbank0vld7reset = ~rst_l | (({que_b0_cmd_picked_d1,que_b0_index_picked_d1} == 4'h7) & 
					~que_scrb_picked_d1 & |que_ras_picked_d1[7:0] &
					(que_channel_picked_internal_d1 == que_channel_disabled));

// Valids

dffrle_ns readqbank0vld0flop (
        .din    (1'b1),
        .q      (readqbank0vld0),
        .rst_l  (~readqbank0vld0reset),
        .en     (rqb0entry0wren),
        .clk    (clk));

dffrle_ns readqbank0vld1flop (
        .din    (1'b1),
        .q      (readqbank0vld1),
        .rst_l  (~readqbank0vld1reset),
        .en     (rqb0entry1wren),
        .clk    (clk));

dffrle_ns readqbank0vld2flop (
        .din    (1'b1),
        .q      (readqbank0vld2),
        .rst_l  (~readqbank0vld2reset),
        .en     (rqb0entry2wren),
        .clk    (clk));

dffrle_ns readqbank0vld3flop (
        .din    (1'b1),
        .q      (readqbank0vld3),
        .rst_l  (~readqbank0vld3reset),
        .en     (rqb0entry3wren),
        .clk    (clk));

dffrle_ns readqbank0vld4flop (
        .din    (1'b1),
        .q      (readqbank0vld4),
        .rst_l  (~readqbank0vld4reset),
        .en     (rqb0entry4wren),
        .clk    (clk));

dffrle_ns readqbank0vld5flop (
        .din    (1'b1),
        .q      (readqbank0vld5),
        .rst_l  (~readqbank0vld5reset),
        .en     (rqb0entry5wren),
        .clk    (clk));

dffrle_ns readqbank0vld6flop (
        .din    (1'b1),
        .q      (readqbank0vld6),
        .rst_l  (~readqbank0vld6reset),
        .en     (rqb0entry6wren),
        .clk    (clk));

dffrle_ns readqbank0vld7flop (
        .din    (1'b1),
        .q      (readqbank0vld7),
        .rst_l  (~readqbank0vld7reset),
        .en     (rqb0entry7wren),
        .clk    (clk));

// Address

dffe_ns #(36) 	readqbank0addr0flop (
        .din    (que_rd_addr0[35:0]),
        .q      (readqbank0addr0[35:0]),
        .en     (rqb0entry0wren),
        .clk    (clk));

dffe_ns #(36) 	readqbank0addr1flop (
        .din    (que_rd_addr0[35:0]),
        .q      (readqbank0addr1[35:0]),
        .en     (rqb0entry1wren),
        .clk    (clk));

dffe_ns #(36) 	readqbank0addr2flop (
        .din    (que_rd_addr0[35:0]),
        .q      (readqbank0addr2[35:0]),
        .en     (rqb0entry2wren),
        .clk    (clk));

dffe_ns #(36) 	readqbank0addr3flop (
        .din    (que_rd_addr0[35:0]),
        .q      (readqbank0addr3[35:0]),
        .en     (rqb0entry3wren),
        .clk    (clk));

dffe_ns #(36) readqbank0addr4flop (
        .din    (que_rd_addr0[35:0]),
        .q      (readqbank0addr4[35:0]),
        .en     (rqb0entry4wren),
        .clk    (clk));

dffe_ns #(36) readqbank0addr5flop (
        .din    (que_rd_addr0[35:0]),
        .q      (readqbank0addr5[35:0]),
        .en     (rqb0entry5wren),
        .clk    (clk));

dffe_ns #(36) readqbank0addr6flop (
        .din    (que_rd_addr0[35:0]),
        .q      (readqbank0addr6[35:0]),
        .en     (rqb0entry6wren),
        .clk    (clk));

dffe_ns #(36) readqbank0addr7flop (
        .din    (que_rd_addr0[35:0]),
        .q      (readqbank0addr7[35:0]),
        .en     (rqb0entry7wren),
        .clk    (clk));

// Request ID

dffe_ns  #(3) readqbank0id0flop (
        .din    (que_rd_id0[2:0]),
        .q      (readqbank0id0[2:0]),
        .en     (rqb0entry0wren),
        .clk    (clk));

dffe_ns  #(3) readqbank0id1flop (
        .din    (que_rd_id0[2:0]),
        .q      (readqbank0id1[2:0]),
        .en     (rqb0entry1wren),
        .clk    (clk));

dffe_ns  #(3) readqbank0id2flop (
        .din    (que_rd_id0[2:0]),
        .q      (readqbank0id2[2:0]),
        .en     (rqb0entry2wren),
        .clk    (clk));

dffe_ns  #(3) readqbank0id3flop (
        .din    (que_rd_id0[2:0]),
        .q      (readqbank0id3[2:0]),
        .en     (rqb0entry3wren),
        .clk    (clk));

dffe_ns  #(3) readqbank0id4flop (
        .din    (que_rd_id0[2:0]),
        .q      (readqbank0id4[2:0]),
        .en     (rqb0entry4wren),
        .clk    (clk));

dffe_ns  #(3) readqbank0id5flop (
        .din    (que_rd_id0[2:0]),
        .q      (readqbank0id5[2:0]),
        .en     (rqb0entry5wren),
        .clk    (clk));

dffe_ns  #(3) readqbank0id6flop (
        .din    (que_rd_id0[2:0]),
        .q      (readqbank0id6[2:0]),
        .en     (rqb0entry6wren),
        .clk    (clk));

dffe_ns  #(3) readqbank0id7flop (
        .din    (que_rd_id0[2:0]),
        .q      (readqbank0id7[2:0]),
        .en     (rqb0entry7wren),
        .clk    (clk));

//////////////////////////////////////////////////////////////////
// Writes Requests for bank0 
//////////////////////////////////////////////////////////////////

assign writeqbank0vld0reset_arb = ~rst_l | 
					(({que_b0_cmd_picked_d1,que_b0_index_picked_d1} == 4'h8) &  
					~que_scrb_picked_d1 & |que_ras_picked_d1[7:0] &
					(que_channel_picked_internal_d1 == que_channel_disabled));
assign writeqbank0vld1reset_arb = ~rst_l | 
					(({que_b0_cmd_picked_d1,que_b0_index_picked_d1} == 4'h9) &  
					~que_scrb_picked_d1 & |que_ras_picked_d1[7:0] &
					(que_channel_picked_internal_d1 == que_channel_disabled));
assign writeqbank0vld2reset_arb = ~rst_l | 
					(({que_b0_cmd_picked_d1,que_b0_index_picked_d1} == 4'ha) &  
					~que_scrb_picked_d1 & |que_ras_picked_d1[7:0] &
					(que_channel_picked_internal_d1 == que_channel_disabled));
assign writeqbank0vld3reset_arb = ~rst_l | 
					(({que_b0_cmd_picked_d1,que_b0_index_picked_d1} == 4'hb) &  
					~que_scrb_picked_d1 & |que_ras_picked_d1[7:0] &
					(que_channel_picked_internal_d1 == que_channel_disabled));
assign writeqbank0vld4reset_arb = ~rst_l | 
					(({que_b0_cmd_picked_d1,que_b0_index_picked_d1} == 4'hc) &  
					~que_scrb_picked_d1 & |que_ras_picked_d1[7:0] &
					(que_channel_picked_internal_d1 == que_channel_disabled));
assign writeqbank0vld5reset_arb = ~rst_l | 
					(({que_b0_cmd_picked_d1,que_b0_index_picked_d1} == 4'hd) &  
					~que_scrb_picked_d1 & |que_ras_picked_d1[7:0] &
					(que_channel_picked_internal_d1 == que_channel_disabled));
assign writeqbank0vld6reset_arb = ~rst_l | 
					(({que_b0_cmd_picked_d1,que_b0_index_picked_d1} == 4'he) &  
					~que_scrb_picked_d1 & |que_ras_picked_d1[7:0] &
					(que_channel_picked_internal_d1 == que_channel_disabled));
assign writeqbank0vld7reset_arb = ~rst_l | 
					(({que_b0_cmd_picked_d1,que_b0_index_picked_d1} == 4'hf) &  
					~que_scrb_picked_d1 & |que_ras_picked_d1[7:0] &
					(que_channel_picked_internal_d1 == que_channel_disabled));

wire [3:0]	que_int_index01_picked;
wire [3:0]	que_index01_picked;
wire		que_cas_ch01_picked;
wire		que_wr_picked;

assign writeqbank0vld0reset = ~rst_l | ((que_index01_picked == 4'h8) & que_wr_picked &
			~que_bypass_scrb_data & (que_cas_ch01_picked == que_channel_disabled));
assign writeqbank0vld1reset = ~rst_l | ((que_index01_picked == 4'h9) & que_wr_picked &
			~que_bypass_scrb_data & (que_cas_ch01_picked == que_channel_disabled));
assign writeqbank0vld2reset = ~rst_l | ((que_index01_picked == 4'hA) & que_wr_picked &
			~que_bypass_scrb_data & (que_cas_ch01_picked == que_channel_disabled));
assign writeqbank0vld3reset = ~rst_l | ((que_index01_picked == 4'hB) & que_wr_picked &
			~que_bypass_scrb_data & (que_cas_ch01_picked == que_channel_disabled));
assign writeqbank0vld4reset = ~rst_l | ((que_index01_picked == 4'hC) & que_wr_picked &
			~que_bypass_scrb_data & (que_cas_ch01_picked == que_channel_disabled));
assign writeqbank0vld5reset = ~rst_l | ((que_index01_picked == 4'hD) & que_wr_picked &
			~que_bypass_scrb_data & (que_cas_ch01_picked == que_channel_disabled));
assign writeqbank0vld6reset = ~rst_l | ((que_index01_picked == 4'hE) & que_wr_picked &
			~que_bypass_scrb_data & (que_cas_ch01_picked == que_channel_disabled));
assign writeqbank0vld7reset = ~rst_l | ((que_index01_picked == 4'hF) & que_wr_picked &
			~que_bypass_scrb_data & (que_cas_ch01_picked == que_channel_disabled));

// Valids for Arbitration only. There are other valids just for incomming write requests.

dffrle_ns writeqbank0vld0flop_arb (
        .din    (1'b1),
        .q      (writeqbank0vld0_arb),
        .rst_l  (~writeqbank0vld0reset_arb),
        .en     (wqb0entry0wren),
        .clk    (clk));

dffrle_ns writeqbank0vld1flop_arb (
        .din    (1'b1),
        .q      (writeqbank0vld1_arb),
        .rst_l  (~writeqbank0vld1reset_arb),
        .en     (wqb0entry1wren),
        .clk    (clk));

dffrle_ns writeqbank0vld2flop_arb (
        .din    (1'b1),
        .q      (writeqbank0vld2_arb),
        .rst_l  (~writeqbank0vld2reset_arb),
        .en     (wqb0entry2wren),
        .clk    (clk));

dffrle_ns writeqbank0vld3flop_arb (
        .din    (1'b1),
        .q      (writeqbank0vld3_arb),
        .rst_l  (~writeqbank0vld3reset_arb),
        .en     (wqb0entry3wren),
        .clk    (clk));

dffrle_ns writeqbank0vld4flop_arb (
        .din    (1'b1),
        .q      (writeqbank0vld4_arb),
        .rst_l  (~writeqbank0vld4reset_arb),
        .en     (wqb0entry4wren),
        .clk    (clk));

dffrle_ns writeqbank0vld5flop_arb (
        .din    (1'b1),
        .q      (writeqbank0vld5_arb),