opensparc ddr2 controller rtl files.v

基于FPGA的DDR2控制程序

wire [7:0]	que_b0_wr_banksel_addr4_dec;
wire [7:0]	que_b0_wr_banksel_addr3_dec;
wire [7:0]	que_b0_wr_banksel_addr5_dec;
wire [7:0]	que_b0_wr_banksel_addr6_dec;
wire [7:0]	que_b0_wr_banksel_addr7_dec;
wire [7:0]	que_b0_indx0_val;
wire [7:0]	que_b0_indx1_val;
wire [7:0]	que_b0_indx2_val;
wire [7:0]	que_b0_indx3_val;
wire [7:0]	que_b0_indx4_val;
wire [7:0]	que_b0_indx5_val;
wire [7:0]	que_b0_indx6_val;
wire [7:0]	que_b0_indx7_val;
wire [7:0]	que_b0_wr_indx0_val;
wire [7:0]	que_b0_wr_indx1_val;
wire [7:0]	que_b0_wr_indx2_val;
wire [7:0]	que_b0_wr_indx3_val;
wire [7:0]	que_b0_wr_indx4_val;
wire [7:0]	que_b0_wr_indx5_val;
wire [7:0]	que_b0_wr_indx6_val;
wire [7:0]	que_b0_wr_indx7_val;
wire [7:0]	que_b0_indx0_val_d1;
wire [7:0]	que_b0_indx1_val_d1;
wire [7:0]	que_b0_indx2_val_d1;
wire [7:0]	que_b0_indx3_val_d1;
wire [7:0]	que_b0_indx4_val_d1;
wire [7:0]	que_b0_indx5_val_d1;
wire [7:0]	que_b0_indx6_val_d1;
wire [7:0]	que_b0_indx7_val_d1;
wire [7:0]	que_b0_wr_indx0_val_d1;
wire [7:0]	que_b0_wr_indx1_val_d1;
wire [7:0]	que_b0_wr_indx2_val_d1;
wire [7:0]	que_b0_wr_indx3_val_d1;
wire [7:0]	que_b0_wr_indx4_val_d1;
wire [7:0]	que_b0_wr_indx5_val_d1;
wire [7:0]	que_b0_wr_indx6_val_d1;
wire [7:0]	que_b0_wr_indx7_val_d1;
wire [7:0]	que_b0_bank_val;
wire [7:0]	que_scrb_bank_valid;
wire [7:0]	que_bank_l2req_valids;
wire [7:0]	que_bank_valids;
wire [3:0]	rrd_cnt_next;
wire [3:0]	rrd_cnt;
wire		rrd_cnt_is_zero;
wire [3:0]	b0_rcd_cnt_next;
wire [3:0]	b0_rcd_cnt;
wire		b0_rcd_cnt_is_zero;
wire [4:0]	b0_rc_cnt_next;
wire [4:0]	b0_rc_cnt;
wire		b0_rc_cnt_is_zero;
wire		b0_ras_pend_req;
wire		b0_ras_picked;
wire		b0_cas_pend_req;
wire		b0_cas_picked;
wire [3:0]	b7_rcd_cnt_next;
wire [3:0]	b7_rcd_cnt;
wire		b7_rcd_cnt_is_zero;
wire [4:0]	b7_rc_cnt_next;
wire [4:0]	b7_rc_cnt;
wire		b7_rc_cnt_is_zero;
wire		b7_ras_pend_req;
wire		b7_ras_picked;
wire		b7_cas_pend_req;
wire		b7_cas_picked;
wire		b1_ras_pend_req;
wire		b2_ras_pend_req;
wire		b3_ras_pend_req;
wire		b4_ras_pend_req;
wire		b5_ras_pend_req;
wire		b6_ras_pend_req;
wire		b1_ras_picked;
wire		b2_ras_picked;
wire		b3_ras_picked;
wire		b4_ras_picked;
wire		b5_ras_picked;
wire		b6_ras_picked;
wire [7:0]	que_cas_valid;
wire [31:0]	b7_cas_info;
wire [31:0]	b6_cas_info;
wire [31:0]	b5_cas_info;
wire [31:0]	b4_cas_info;
wire [31:0]	b3_cas_info;
wire [31:0]	b2_cas_info;
wire [31:0]	b1_cas_info;
wire [31:0]	b0_cas_info;
wire		b1_cas_pend_req;
wire		b2_cas_pend_req;
wire		b3_cas_pend_req;
wire		b4_cas_pend_req;
wire		b5_cas_pend_req;
wire		b6_cas_pend_req;
wire		b1_cas_picked;
wire		b2_cas_picked;
wire		b3_cas_picked;
wire		b4_cas_picked;
wire		b5_cas_picked;
wire		b6_cas_picked;
wire [7:0]	que_ras_picked;
wire [7:0]	que_ras_picked_d1;
wire [7:0]	que_ras_picked_io_d1;
wire		que_b0_index0_picked;
wire		que_b0_index1_picked;
wire		que_b0_index2_picked;
wire		que_b0_index3_picked;
wire		que_b0_index4_picked;
wire		que_b0_index5_picked;
wire		que_b0_index6_picked;
wire		que_b0_index7_picked;
wire		que_b0_wr_index0_picked;
wire		que_b0_wr_index1_picked;
wire		que_b0_wr_index2_picked;
wire		que_b0_wr_index3_picked;
wire		que_b0_wr_index4_picked;
wire		que_b0_wr_index5_picked;
wire		que_b0_wr_index6_picked;
wire		que_b0_wr_index7_picked;
wire [2:0]	que_b0_index_picked;
wire [35:0]	que_b0_addr_picked;
wire [2:0]	que_b0_id_picked;
wire		que_b0_cmd_picked;
wire [2:0]	que_id_picked;
wire		que_cmd_picked;
wire [14:0]	que_ras_adr;
wire [13:0]	que_cas_adr;
wire [2:0]	que_bank_adr;
wire [14:0]	que_mux_cas_adr;
wire [2:0]	que_mux_bank_adr;
wire [6:0]	mode_reg_in;
wire [6:0]	mode_reg;
wire [14:0]	ext_mode_reg1_in;
wire [14:0]	ext_mode_reg1;
wire [14:0]	ext_mode_reg2_in;
wire [14:0]	ext_mode_reg2;
wire [14:0]	ext_mode_reg3_in;
wire [14:0]	ext_mode_reg3;
wire [8:0]	que_b0_index_ent0;
wire [8:0]	que_b0_index_ent1;
wire [8:0]	que_b0_index_ent2;
wire [8:0]	que_b0_index_ent3;
wire [8:0]	que_b0_index_ent4;
wire [8:0]	que_b0_index_ent5;
wire [8:0]	que_b0_index_ent6;
wire [8:0]	que_b0_index_ent7;
wire [35:0]	readqbank0addr0;
wire [35:0]	readqbank0addr1;
wire [35:0]	readqbank0addr2;
wire [35:0]	readqbank0addr3;
wire [35:0]	readqbank0addr4;
wire [35:0]	readqbank0addr5;
wire [35:0]	readqbank0addr6;
wire [35:0]	readqbank0addr7;
wire [35:0]	writeqbank0addr0;
wire [35:0]	writeqbank0addr1;
wire [35:0]	writeqbank0addr2;
wire [35:0]	writeqbank0addr3;
wire [35:0]	writeqbank0addr4;
wire [35:0]	writeqbank0addr5;
wire [35:0]	writeqbank0addr6;
wire [35:0]	writeqbank0addr7;
wire [2:0]	writeqaddr0;
wire [2:0]	writeqaddr1;
wire [2:0]	writeqaddr2;
wire [2:0]	writeqaddr3;
wire [2:0]	writeqaddr4;
wire [2:0]	writeqaddr5;
wire [2:0]	writeqaddr6;
wire [2:0]	writeqaddr7;
wire [2:0]	readqbank0id0;
wire [2:0]	readqbank0id1;
wire [2:0]	readqbank0id2;
wire [2:0]	readqbank0id3;
wire [2:0]	readqbank0id4;
wire [2:0]	readqbank0id5;
wire [2:0]	readqbank0id6;
wire [2:0]	readqbank0id7;
wire		que_bank0_cas_valid;
wire		que_bank1_cas_valid;
wire		que_bank2_cas_valid;
wire		que_bank3_cas_valid;
wire		que_bank4_cas_valid;
wire		que_bank5_cas_valid;
wire		que_bank6_cas_valid;
wire		que_bank7_cas_valid;
wire		que_bank0_cas_en;
wire		que_bank1_cas_en;
wire		que_bank2_cas_en;
wire		que_bank3_cas_en;
wire		que_bank4_cas_en;
wire		que_bank5_cas_en;
wire		que_bank6_cas_en;
wire		que_bank7_cas_en;

wire [3:0]	b1_rcd_cnt_next;
wire [3:0]	b1_rcd_cnt;
wire [4:0]	b1_rc_cnt_next;
wire [4:0]	b1_rc_cnt;
wire		b1_rc_cnt_is_zero;
wire		b1_rcd_cnt_is_zero;

wire [3:0]	b2_rcd_cnt_next;
wire [3:0]	b2_rcd_cnt;
wire [4:0]	b2_rc_cnt_next;
wire [4:0]	b2_rc_cnt;
wire		b2_rc_cnt_is_zero;
wire		b2_rcd_cnt_is_zero;

wire [3:0]	b3_rcd_cnt_next;
wire [3:0]	b3_rcd_cnt;
wire [4:0]	b3_rc_cnt_next;
wire [4:0]	b3_rc_cnt;
wire		b3_rc_cnt_is_zero;
wire		b3_rcd_cnt_is_zero;

wire [3:0]	b4_rcd_cnt_next;
wire [3:0]	b4_rcd_cnt;
wire [4:0]	b4_rc_cnt_next;
wire [4:0]	b4_rc_cnt;
wire		b4_rc_cnt_is_zero;
wire		b4_rcd_cnt_is_zero;

wire [3:0]	b5_rcd_cnt_next;
wire [3:0]	b5_rcd_cnt;
wire [4:0]	b5_rc_cnt_next;
wire [4:0]	b5_rc_cnt;
wire		b5_rc_cnt_is_zero;
wire		b5_rcd_cnt_is_zero;

wire [3:0]	b6_rcd_cnt_next;
wire [3:0]	b6_rcd_cnt;
wire [4:0]	b6_rc_cnt_next;
wire [4:0]	b6_rc_cnt;
wire		b6_rc_cnt_is_zero;
wire		b6_rcd_cnt_is_zero;

wire [3:0]	rrd_reg;
wire [3:0]	rcd_reg;
wire [4:0]	rc_reg;
wire [3:0]	rrd_reg_in;
wire [3:0]	rcd_reg_in;
wire [4:0]	rc_reg_in;

wire [3:0]	que_b0_data_rtn_cnt;
wire [3:0]	que_b1_data_rtn_cnt;
wire [3:0]	que_b2_data_rtn_cnt;
wire [3:0]	que_b3_data_rtn_cnt;
wire [3:0]	que_b4_data_rtn_cnt;
wire [3:0]	que_b5_data_rtn_cnt;
wire [3:0]	que_b6_data_rtn_cnt;
wire [3:0]	que_b7_data_rtn_cnt;

wire 		que_burst_wr_cnt;
wire 		que_burst_wr_cnt_in;
wire		que_burst_write_cnt_en;
wire [2:0]	que_wr_addr_b0;

wire [3:0]	wtr_reg_in;
wire [3:0]	wtr_reg;
wire [3:0]	wtr_dly_reg;
wire [1:0]	iwtr_reg_in;
wire [1:0]	iwtr_reg;

wire [3:0]	wtr_cnt_next;
wire [3:0]	wtr_cnt;
wire		wtr_cnt_is_zero;
wire 		rtr_cnt_next;
wire 		rtr_cnt;
wire		rtr_cnt_is_zero;
wire 		wtw_cnt_next;
wire 		wtw_cnt;
wire		wtw_cnt_is_zero;
wire [6:0]	rfc_cnt_next;
wire [6:0]	rfc_cnt;
wire		rfc_cnt_is_zero;
wire		mrd_cnt_is_zero;

wire [3:0]	rp_reg;
wire [3:0]	wr_reg;
wire [6:0]	rfc_reg;

wire [3:0]	b0_dal_cnt_next;
wire [3:0]	b0_dal_cnt;
wire		b0_dal_cnt_is_zero;
wire [3:0]	b1_dal_cnt_next;
wire [3:0]	b1_dal_cnt;
wire		b1_dal_cnt_is_zero;
wire [3:0]	b2_dal_cnt_next;
wire [3:0]	b2_dal_cnt;
wire		b2_dal_cnt_is_zero;
wire [3:0]	b3_dal_cnt_next;
wire [3:0]	b3_dal_cnt;
wire		b3_dal_cnt_is_zero;
wire [3:0]	b4_dal_cnt_next;
wire [3:0]	b4_dal_cnt;
wire		b4_dal_cnt_is_zero;
wire [3:0]	b5_dal_cnt_next;
wire [3:0]	b5_dal_cnt;
wire		b5_dal_cnt_is_zero;
wire [3:0]	b6_dal_cnt_next;
wire [3:0]	b6_dal_cnt;
wire		b6_dal_cnt_is_zero;
wire [3:0]	b7_dal_cnt_next;
wire [3:0]	b7_dal_cnt;
wire		b7_dal_cnt_is_zero;
wire [3:0]	dal_reg;
wire [3:0]	ral_reg;
wire [2:0]	que_index_picked;
wire		writeqbank0vld0reset_arb;
wire		writeqbank0vld1reset_arb;
wire		writeqbank0vld2reset_arb;
wire		writeqbank0vld3reset_arb;
wire		writeqbank0vld4reset_arb;
wire		writeqbank0vld5reset_arb;
wire		writeqbank0vld6reset_arb;
wire		writeqbank0vld7reset_arb;
wire [63:0]	que_ucb_data;
wire [31:0]	que_ucb_addr;
wire [35:0]	que_err_addr_reg;
wire [22:0]	que_err_sts_reg;
wire [2:0]	que_cpu_wr_addr;
wire [35:0]	que_rd_addr0;
wire [35:0]	que_wr_addr0;
wire [2:0]	que_rd_id0;
wire [35:0]	que_err_loc;
wire [17:0]	que_err_cnt;
wire [2:0]	que_b0_index_picked_d1;
wire		que_channel_picked_internal;

//////////////////////////////////////////////////////////////////
// Flopping the cpu domain signals to dram domain
//////////////////////////////////////////////////////////////////
dff_ns #(2) ff_rd_wr_val(
        .din    ({l2if_wr_req, l2if_rd_req}),
        .q      ({que_wr_req, que_rd_req}),
        .clk    (clk));

dff_ns #(3) ff_rd_id(
        .din    (l2if_rd_id),
        .q      (que_rd_id0),
        .clk    (clk));

dff_ns #(72) ff_rd_wr_addr(
        .din    ({l2if_rd_addr, l2if_wr_addr}),
        .q      ({que_rd_addr0, que_wr_addr0}),
        .clk    (clk));

dff_ns #(98) ff_ucb_req(
        .din    ({l2if_que_rd_req_vld, l2if_que_wr_req_vld, l2if_que_addr[31:0], 
			l2if_que_data[63:0]}),
        .q    ({que_ucb_rd_req_vld, que_ucb_wr_req_vld, que_ucb_addr[31:0], 
			que_ucb_data[63:0]}),
        .clk    (clk));

dff_ns #(60) ff_err1_regs(
        .din    ({l2if_dbg_trig_en, l2if_err_addr_reg[35:0], l2if_err_sts_reg[22:0]}),
        .q      ({que_dbg_trig_en, que_err_addr_reg[35:0], que_err_sts_reg[22:0]}),
        .clk    (clk));

dff_ns #(54) ff_err2_regs(
        .din    ({l2if_err_loc[35:0], l2if_err_cnt[17:0]}),
        .q      ({que_err_loc[35:0], que_err_cnt[17:0]}),
        .clk    (clk));

dff_ns #(3) ff_wr_index0(
        .din    (l2if_data_wr_addr[2:0]),
        .q      (que_cpu_wr_addr[2:0]),