opensparc ddr2 controller rtl files.v

基于FPGA的DDR2控制程序

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T1 Processor File: dram_que.v
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
// 
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
// 
// The above named program is distributed in the hope that it will be 
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
// General Public License for more details.
// 
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
// 
// ========== Copyright Header End ============================================

[Up: dram_dctl dram_que]
module dram_queIndex (/*AUTOARG*/
   // Outputs
   que_margin_reg, readqbank0vld0, readqbank0vld1, readqbank0vld2, 
   readqbank0vld3, writeqbank0vld0, writeqbank0vld1, writeqbank0vld2, 
   writeqbank0vld3, readqbank0vld4, readqbank0vld5, readqbank0vld6, 
   readqbank0vld7, writeqbank0vld4, writeqbank0vld5, writeqbank0vld6, 
   writeqbank0vld7, que_scrb_addr, dram_fail_over_mode, 
   que_wr_entry_free, config_reg, que_rank1_present, 
   que_addr_bank_low_sel, dram_io_pad_enable, dram_io_addr, 
   dram_io_bank, dram_io_cs_l, dram_io_ras_l, dram_io_cas_l, 
   dram_io_cke, dram_io_write_en_l, dram_io_drive_enable, 
   dram_io_drive_data, dram_io_clk_enable, dram_io_pad_clk_inv, 
   dram_io_ptr_clk_inv, dram_io_channel_disabled, 
   dram_fail_over_mask, que_mem_addr, que_bypass_scrb_data, 
   que_l2if_ack_vld, que_l2if_nack_vld, que_l2if_data, 
   que_dram_clk_toggle, dram_local_pt_opened_bank, 
   que_max_banks_open_valid, que_max_banks_open, que_max_time_valid, 
   err_inj_reg, err_mask_reg, que_st_cmd_addr_parity, 
   que_cas_int_picked, que_wr_cas_ch01_picked, que_mux_write_en, 
   que_l2if_send_info, que_ras_int_picked, que_b0_data_addr, 
   que_l2req_valids, que_b0_addr_picked, que_b0_id_picked, 
   que_b0_index_picked, que_b0_cmd_picked, que_channel_picked, 
   que_int_wr_que_inv_info, que_int_pos, que_channel_disabled, 
   que_wr_channel_mux, que_eight_bank_mode, 
   // Inputs
   clk, rst_l, l2if_que_selfrsh, dram_dbginit_l, l2if_rd_id, l2if_rd_addr, 
   l2if_wr_addr, l2if_wr_req, l2if_rd_req, l2if_que_rd_req_vld, 
   l2if_que_wr_req_vld, l2if_que_addr, l2if_que_data, 
   pt_ch_blk_new_openbank, pt_max_banks_open, pt_max_time, 
   l2if_data_wr_addr, l2if_err_addr_reg, l2if_err_sts_reg, 
   l2if_err_loc, l2if_err_cnt, l2if_dbg_trig_en, sehold,
   ch0_que_cas_int_picked, ch0_que_wr_cas_ch01_picked, 
   ch0_que_mux_write_en, ch0_que_ras_int_picked, arst_l,
   ch0_que_b0_data_addr, ch0_que_channel_picked, 
   ch1_que_l2req_valids, ch1_que_b0_addr_picked, 
   ch1_que_b0_id_picked, ch1_que_b0_index_picked, 
   ch1_que_b0_cmd_picked, other_que_channel_disabled, other_que_pos, 
   ch1_que_int_wr_que_inv_info, que_wr_req, sshot_err_reg
   );

// DRAM controller  interface
input 		clk;
input 		rst_l;
input 		arst_l;
input 		sehold;
input		l2if_que_selfrsh;
input		dram_dbginit_l;
output [4:0]	que_margin_reg;

// rd interface
input [2:0]  	l2if_rd_id;
input [35:0]   	l2if_rd_addr;
input [35:0]   	l2if_wr_addr;

// Valids from cpu to dram clk domain
input          	l2if_wr_req;
input          	l2if_rd_req;

// from dram to cpu clk domain
output		readqbank0vld0;
output		readqbank0vld1;
output		readqbank0vld2;
output		readqbank0vld3;
output		writeqbank0vld0;
output		writeqbank0vld1;
output		writeqbank0vld2;
output		writeqbank0vld3;
output		readqbank0vld4;
output		readqbank0vld5;
output		readqbank0vld6;
output		readqbank0vld7;
output		writeqbank0vld4;
output		writeqbank0vld5;
output		writeqbank0vld6;
output		writeqbank0vld7;
output		que_wr_req;

output [32:0]	que_scrb_addr;
output		dram_fail_over_mode;
output [3:0]	que_wr_entry_free;
output [8:0]	config_reg;
output		que_rank1_present;
output		que_addr_bank_low_sel;

// PAD interface
output		dram_io_pad_enable;
output [14:0]   dram_io_addr;   
output [2:0]    dram_io_bank;
output [3:0]    dram_io_cs_l;
output          dram_io_ras_l;
output          dram_io_cas_l;
output 		dram_io_cke;
output          dram_io_write_en_l;
output          dram_io_drive_enable;
output          dram_io_drive_data;
output		dram_io_clk_enable;
output 		dram_io_pad_clk_inv;
output [4:0]	dram_io_ptr_clk_inv;
output		dram_io_channel_disabled;

// DP interface
output [34:0]	dram_fail_over_mask;

// Store data interface
output [4:0]	que_mem_addr;

// capture scrub data enable
output		que_bypass_scrb_data;

// FROM L2if
input         	l2if_que_rd_req_vld;
input         	l2if_que_wr_req_vld;
input [31:0]  	l2if_que_addr;
input [63:0]    l2if_que_data;

// TO l2if
output          que_l2if_ack_vld;
output          que_l2if_nack_vld;
output [63:0] 	que_l2if_data;

// FROM CAS INFO
output		que_dram_clk_toggle;

// FROM POWER THROTTLE
output          dram_local_pt_opened_bank;
output		que_max_banks_open_valid;
output [16:0]   que_max_banks_open;
output		que_max_time_valid;

input          	pt_ch_blk_new_openbank;
input [16:0]    pt_max_banks_open;
input [15:0]    pt_max_time;

// TO DP
output		err_inj_reg;
output [15:0]	err_mask_reg;
output		que_st_cmd_addr_parity;

// FROM L2IF
input [2:0]	l2if_data_wr_addr;
input [35:0]    l2if_err_addr_reg;
input [22:0]    l2if_err_sts_reg;
input [35:0]	l2if_err_loc;
input [17:0]	l2if_err_cnt;
input 		l2if_dbg_trig_en;

// NEW ADDITION DUE TO 2 CHANNEL MODE
input [7:0]	ch0_que_cas_int_picked;
input		ch0_que_wr_cas_ch01_picked;
input		ch0_que_mux_write_en;
input [7:0]	ch0_que_ras_int_picked;
input [5:0]	ch0_que_b0_data_addr;
input		ch0_que_channel_picked;
input [7:0]    	ch1_que_l2req_valids;
input [35:0]   	ch1_que_b0_addr_picked;
input [2:0]    	ch1_que_b0_id_picked;
input [2:0]    	ch1_que_b0_index_picked;
input          	ch1_que_b0_cmd_picked;
input		other_que_channel_disabled;
input [4:0]	other_que_pos;
input [6:0]	ch1_que_int_wr_que_inv_info;

output [7:0]	que_cas_int_picked;
output		que_wr_cas_ch01_picked;
output		que_mux_write_en;
output [9:0]  	que_l2if_send_info;
output [7:0]	que_ras_int_picked;
output [5:0]	que_b0_data_addr;
output [7:0]	que_l2req_valids;
output [35:0]	que_b0_addr_picked;
output [2:0]	que_b0_id_picked;
output [2:0]	que_b0_index_picked;
output 		que_b0_cmd_picked;
output		que_channel_picked;
output [6:0]	que_int_wr_que_inv_info;

output [4:0]	que_int_pos;
output		que_channel_disabled;
output		que_wr_channel_mux;
output		que_eight_bank_mode;

output sshot_err_reg;

//////////////////////////////////////////////////////////////////
// Wires
//////////////////////////////////////////////////////////////////
wire [11:0]	que_cl2_stg_info;
wire [11:0]	que_cl3_stg_info;
wire [11:0]	que_cl4_stg_info;
wire [11:0]	que_cl5_stg_info;
wire [7:0]	b0_cas_cnt;
wire [7:0]	b1_cas_cnt;
wire [7:0]	b2_cas_cnt;
wire [7:0]	b3_cas_cnt;
wire [7:0]	b4_cas_cnt;
wire [7:0]	b5_cas_cnt;
wire [7:0]	b6_cas_cnt;
wire [7:0]	b7_cas_cnt;
wire [7:0]	b0_cas_cnt_in;
wire [7:0]	b1_cas_cnt_in;
wire [7:0]	b2_cas_cnt_in;
wire [7:0]	b3_cas_cnt_in;
wire [7:0]	b4_cas_cnt_in;
wire [7:0]	b5_cas_cnt_in;
wire [7:0]	b6_cas_cnt_in;
wire [7:0]	b7_cas_cnt_in;
wire [7:0]	que_perf_cntl_reg;
wire [31:0]	que_perf_cnt0_reg;
wire [31:0]	que_perf_cnt1_reg;
wire 		que_rd_xaction_picked;
wire 		que_wr_xaction_picked;
wire 		que_rd_or_wr_xaction_picked_d1;
wire 		que_bank_busy_stall;
wire 		que_writeback_buf_hit;
wire [3:0] 	que_rd_que_latency;
wire [3:0] 	que_wr_que_latency;
wire [3:0] 	que_rd_que_latency_d1;
wire [3:0] 	que_wr_que_latency_d1;
wire [4:0] 	que_rd_or_wr_que_latency_d1;
wire		two_channel_mode;
wire		que_prev_scrb_wr_pending;
wire [3:0]	que_tot_data_del_cnt;
wire [8:0]	que_l2_send_id;
wire		que_init_dram_done;
wire [35:0]	que_split_scrb_addr;
wire [1:0]	que_refresh_rank;
wire [2:0]	que_refresh_rank_cnt;
wire		que_scrb_stack_addr;
wire [9:0]	que_l2if_send_info_in;
wire [1:0]	que_phy_bank_picked;
wire		que_b0_rd_picked;
wire [32:0]	que_scrb_addr_p1;
wire [2:0]	que_b0_wr_data_addr_picked;
wire		que_rank1_present;
wire		que_scrb_rank_addr;
wire		que_mux_rank_adr;
wire		que_phy_bank_wait;
wire		que_rank_picked;
wire		dram_io_pad_enable_in;
wire [2:0]	que_data_del_cnt_in;
wire [2:0]	que_data_del_cnt;
wire		dram_io_sw_mux_cnt_en;
wire [1:0]      dram_io_sw_mux_cnt_in;
wire [1:0]      dram_io_sw_mux_cnt;
wire		que_init_en;
wire		que_init_in;
wire		que_init;
wire		que_ack_vld_in;
wire		que_nack_vld_in;
wire		que_b0_wr_index_pend;
wire [12:0]	que_ref_cnt_166_200;
wire [12:0]	que_ref_cnt_166_200_in;
wire		que_scrb_write_req;
wire		que_scrb_write_valid;
wire		que_scrb_read_valid;
wire [11:0]	que_scrb_cnt_in;
wire [11:0]	que_scrb_cnt;
wire		que_scrb_cnt_reset;
wire		que_scrb_time;
wire		que_scrb_read_en;
wire [8:0]	que_scrb_cas_addr_in;
wire [8:0]	que_scrb_cas_addr;
wire [14:0]	que_scrb_ras_addr_in;
wire [14:0]	que_scrb_ras_addr;
wire [2:0]	que_scrb_bank_in;
wire [2:0]	que_scrb_bank;
wire		que_scrb_picked;
wire		que_scrb_rd_picked;
wire		rp_cnt_is_zero;
wire [4:0]	que_int_pos;
wire [4:0]	que_pos;
wire		que_po_ras_l;
wire		que_po_cas_l;
wire		que_po_write_en_l;
wire [3:0]	que_po_cs_l;
wire [2:0]	que_po_bank;
wire [14:0]	que_po_addr;
wire		que_po_ras_l_p1;
wire		que_po_cas_l_p1;
wire [3:0]	que_po_cs_l_p1;
wire		que_po_write_en_l_p1;
wire [2:0]	que_po_bank_p1;
wire [14:0]	que_po_addr_p1;
wire		dram_io_cke_p1;
wire		que_mux_special_data;
wire		que_refresh_req_picked;
wire		que_dram_clk_toggle_in;
wire [7:0]      que_cas_picked_d1;
wire [7:0]      que_cas_picked_io_d1;
wire 		que_cas_picked;
wire		que_b0_rdq_full;
wire		que_b0_wrq_full;
wire		que_write_en_int;
wire		que_drive_dqs_1f;
wire            sch_mode_reg_en;
wire [20:0]     chip_config_reg_in;
wire		rqb0entry0wren;
wire		rqb0entry1wren;
wire		rqb0entry2wren;
wire		rqb0entry3wren;
wire		rqb0entry4wren;
wire		rqb0entry5wren;
wire		rqb0entry6wren;
wire		rqb0entry7wren;
wire		wqb0entry0wren;
wire		wqb0entry1wren;
wire		wqb0entry2wren;
wire		wqb0entry3wren;
wire		wqb0entry4wren;
wire		wqb0entry5wren;
wire		wqb0entry6wren;
wire		wqb0entry7wren;
wire		readqbank0vld0reset;
wire		readqbank0vld1reset;
wire		readqbank0vld2reset;
wire		readqbank0vld3reset;
wire		readqbank0vld4reset;
wire		readqbank0vld5reset;
wire		readqbank0vld6reset;
wire		readqbank0vld7reset;
wire		writeqbank0vld0reset;
wire		writeqbank0vld1reset;
wire		writeqbank0vld2reset;
wire		writeqbank0vld3reset;
wire		writeqbank0vld4reset;
wire		writeqbank0vld5reset;
wire		writeqbank0vld6reset;
wire		writeqbank0vld7reset;
wire [7:0]	que_b0_rd_index;
wire [7:0]	que_b0_wr_index;
wire		que_b0_index_en;
wire [20:0]	chip_config_reg;
wire [7:0]	que_b0_banksel_addr0_dec;
wire [7:0]	que_b0_banksel_addr1_dec;
wire [7:0]	que_b0_banksel_addr2_dec;
wire [7:0]	que_b0_banksel_addr4_dec;
wire [7:0]	que_b0_banksel_addr3_dec;
wire [7:0]	que_b0_banksel_addr5_dec;
wire [7:0]	que_b0_banksel_addr6_dec;
wire [7:0]	que_b0_banksel_addr7_dec;
wire [7:0]	que_b0_wr_banksel_addr0_dec;
wire [7:0]	que_b0_wr_banksel_addr1_dec;
wire [7:0]	que_b0_wr_banksel_addr2_dec;