_primary.vhd

来自「Viterbi decoder source code」· VHDL 代码 · 共 43 行

library verilog;
use verilog.vl_types.all;
entity viterbi_k7_inst is
    port(
        clk1p           : in     vl_logic;
        decodestart     : in     vl_logic;
        pwrreset        : in     vl_logic;
        g3              : in     vl_logic_vector(2 downto 0);
        g2              : in     vl_logic_vector(2 downto 0);
        g1              : in     vl_logic_vector(2 downto 0);
        g0              : in     vl_logic_vector(2 downto 0);
        outstart        : out    vl_logic;
        serialout       : out    vl_logic;
        syncsel         : out    vl_logic_vector(1 downto 0);
        startsync       : out    vl_logic;
        gs0             : out    vl_logic_vector(2 downto 0);
        gs1             : out    vl_logic_vector(2 downto 0);
        gs2             : out    vl_logic_vector(2 downto 0);
        gs3             : out    vl_logic_vector(2 downto 0);
        pmtoggle        : out    vl_logic;
        enablew_rn      : out    vl_logic;
        bm0             : out    vl_logic_vector(4 downto 0);
        d0_32           : out    vl_logic_vector(1 downto 0);
        survmemwe       : out    vl_logic;
        survmemoutenab  : out    vl_logic;
        survmemaddr     : out    vl_logic_vector(6 downto 0);
        survmemdata0    : out    vl_logic_vector(31 downto 0);
        survmemdata1    : out    vl_logic_vector(31 downto 0);
        survmemdata2    : out    vl_logic_vector(31 downto 0);
        survmemdata3    : out    vl_logic_vector(31 downto 0);
        tbdecodemsb     : out    vl_logic;
        tbshiftreg      : out    vl_logic_vector(5 downto 0);
        tbdata0         : out    vl_logic_vector(31 downto 0);
        tbdata1         : out    vl_logic_vector(31 downto 0);
        tbdata2         : out    vl_logic_vector(31 downto 0);
        tbdata3         : out    vl_logic_vector(31 downto 0);
        decodebits      : out    vl_logic_vector(3 downto 0);
        lifowe          : out    vl_logic;
        lifooutenab     : out    vl_logic;
        lifoq           : out    vl_logic_vector(3 downto 0)
    );
end viterbi_k7_inst;