ramio96x128_inst.v

来自「Viterbi decoder source code」· Verilog 代码 · 共 8 行

RAMIO96x128	RAMIO96x128_inst (
	.address ( address_sig ),
	.we ( we_sig ),
	.inclock ( inclock_sig ),
	.outenab ( outenab_sig ),
	.dio ( dio_sig )
	);