_primary.vhd

来自「Viterbi decoder source code」· VHDL 代码 · 共 27 行

library verilog;
use verilog.vl_types.all;
entity apex20ke_asynch_mem is
    generic(
        logical_ram_depth : integer := 2048;
        infile           : string  := "xxx";
        address_width    : integer := 16;
        deep_ram_mode    : string  := "off";
        first_address    : integer := 0;
        last_address     : integer := 2047;
        mem1             : integer := 0;
        mem2             : integer := 0;
        mem3             : integer := 0;
        mem4             : integer := 0;
        bit_number       : integer := 0
    );
    port(
        datain          : in     vl_logic;
        we              : in     vl_logic;
        re              : in     vl_logic;
        raddr           : in     vl_logic_vector(15 downto 0);
        waddr           : in     vl_logic_vector(15 downto 0);
        modesel         : in     vl_logic_vector(17 downto 0);
        dataout         : out    vl_logic
    );
end apex20ke_asynch_mem;