_primary.vhd

来自「Viterbi decoder source code」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity pdff is
    generic(
        width            : integer := 1
    );
    port(
        data            : in     vl_logic_vector;
        qout            : out    vl_logic_vector;
        clock           : in     vl_logic;
        reset           : in     vl_logic
    );
end pdff;